PRT2011CVL5A datasheet(53/112 Pages) NXP

tên linh kiện	PRT2011CVL5A

Giải thích chi tiết về linh kiện	i.MX RT1064 Crossover Processors Data Sheet for Consumer Products

PDF	112 Pages

Scroll/Zoom	100%

nhà sản xuất	NXP [NXP Semiconductors]

Trang chủ	http://www.nxp.com

Logo

53 / 112 page

Electrical Characteristics

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020

NXP Semiconductors

Figure 26. FlexSPI output timing in DDR mode

4.6

Display and graphics

The following sections provide information on display and graphic interfaces.

4.6.1

CMOS Sensor Interface (CSI) timing parameters

The following sections describe the CSI timing in gated and ungated clock modes.

4.6.1.0.1

Gated clock mode timing

Figure 27 and Figure 28 shows the gated clock mode timings for CSI, and Table 47 describes the timing

parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC

(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,

CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.

Figure 27. CSI Gated clock mode—sensor data at falling edge, latch data at rising edge

T CSS

T CK

TDVO

TDHO

TDVO

TDHO

TCSH

SCK

SIO[0:7]

CSI_PIXCLK

CSI_VSYNC

CSI_DATA[23:00]

CSI_HSYNC

PRT2011CVL5A bảng dữ liệu(PDF) 53 Page - NXP Semiconductors