PRT2011CVL5A datasheet(59/112 Pages) NXP

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Electrical Characteristics

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020

NXP Semiconductors

Figure 33. SPDIF_SR_CLK timing diagram

Figure 34. SPDIF_ST_CLK timing diagram

4.8

Analog

The following sections provide information about analog interfaces.

4.8.1

DCDC

Table 53 introduces the DCDC electrical specifications.

SPDIF_SR_CLK high period

srckph

16.0

—

SPDIF_SR_CLK low period

srckpl

16.0

—

Modulating Tx clock (SPDIF_ST_CLK) period

stclkp

40.0

—

SPDIF_ST_CLK high period

stclkph

16.0

—

SPDIF_ST_CLK low period

stclkpl

16.0

—

Table 53. DCDC electrical specifications

Mode

Buck mode, one output

Notes

Input voltage

3.3 V

Min = 2.8 V, Max = 3.6 V

Output voltage

1.1 V

Configurable 0.8 - 1.575 with 25 mV one step

in Run mode

Max loading

500 mA

—

Loading in low power modes

200

A ~ 30 mA

—

Table 52. SPDIF timing parameters (continued)

Characteristics

Symbol

Timing Parameter Range

Unit

Min

Max

SPDIF_SR_CLK

(Output)

srckp

srckph

srckpl

SPDIF_ST_CLK

(Input)

stclkp

stclkph

stclkpl

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