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FXLS8964AF bảng dữ liệu(PDF) 83 Page - NXP Semiconductors |
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FXLS8964AF bảng dữ liệu(HTML) 83 Page - NXP Semiconductors |
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83 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Objective data sheet Rev. 2 — 30 October 2020 83 / 98 The scaling for this register is always the same as the selected FSR's sensitivity. See Section 9.4 for the sensitivity values corresponding to each of the selectable FSRs. Table 113. SDCD_UTHS_MSB register (address 36h) bit allocation Bit 7 6 5 4 3 2 1 0 Name — — — — SDCD_UTHS[11:8] Reset (BT_MODE = GND) 0 0 0 0 0 0 0 0 Reset (BT_MODE = VDD) 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 114. SDCD_UTHS_MSB register (address 36h) bit description Field Description 3:0 SDCD_UTHS[11:8] MSB (nibble) of the signed 12-bit 2's complement upper-threshold value 13.32 SELF_TEST_CONFIG1 register (address 37h) Table 115. SELF_TEST_CONFIG1 register (address 37h) bit allocation Bit 7 6 5 4 3 2 1 0 Name — — — ST_IDLE[4:0] Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 116. SELF_TEST_CONFIG1 register (address 37h) bit description Field Description 4:0 ST_IDLE Self-Test Idle phase duration: The value contained in ST_IDLE determines the Self-Test Idle phase duration per the following equation: STIDLE = 312.5 µs + (ST_IDLE * 31.25) µs 13.33 SELF_TEST_CONFIG2 register (address 38h) Table 117. SELF_TEST_CONFIG2 register (address 38h) bit allocation Bit 7 6 5 4 3 2 1 0 Name — — — — ST_DEC[3:0] Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W |
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