FXLS8964AF datasheet(70/98 Pages) NXP

70 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

70 / 98

13.28 ORIENT_DBCOUNT register (address 2Ah)

The

ORIENT_DBCOUNT register sets the debounce count used for validating an

orientation state change. The debounce counter period is determined by the selected

ODR in LPM and HPM modes, and by the effective ODR when operating in FPM. The

minimum debounce latency time is determined by ODR–1 *

ORIENT_DBCOUNT[7:0].

For example, with an ODR of 100 Hz and debounce count value of 10, the new

orientation must be maintained for 100 ms before it is recognized as a valid orientation

and

ORIENT_STATUS[NEW_ORIENT] is asserted. A transition from Standby to Active,

a transition from Active to Standby, or a change in the auto-WAKE/SLEEP mode resets

the internal orientation debounce counter.

Table 85. ORIENT_DBCOUNT register (address 2Ah) bit allocation

Bit

Name

ORIENT_DBCOUNT[7:0]

Reset

Access

R/W

Table 86. ORIENT_DBCOUNT register (address 2Ah) bit description

Field

Description

7:0

ORIENT_

DBCOUNT[7:0]

8-bit unsigned orientation debounce counter value

A new orientation must be maintained for the minimum number of ODR periods specified

in order for the orientation to be considered valid before asserting the

ORIENT_

STATUS[NEW_ORIENT] event flag.

The counter behavior is controlled by

ORIENT_CONFIG[ORIENT_DBCNTM].

The debounce counter period is determined by the selected ODR in LPM and HPM modes,

and by the effective ODR when operating if FPM. The minimum debounce latency time is

determined by:

Debounce_time = (ODR–1 * ORIENT_DBCOUNT) (s)

Note: If the applied acceleration is greater than 1.25 g on any axis, the debounce counter is

held at the current value (frozen).

13.29 ORIENT_BF_ZCOMP register (address 2Bh)

Orientation back/front and Z-tilt angle compensation register

Table 87. ORIENT_BF_ZCOMP register (address 2Bh) bit allocation

Bit

Name

ORIENT_BKFR[1:0]

—

ORIENT_ZLOCK[2:0]

Reset

Access

R/W

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