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FXLS8964AF bảng dữ liệu(PDF) 24 Page - NXP Semiconductors |
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FXLS8964AF bảng dữ liệu(HTML) 24 Page - NXP Semiconductors |
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24 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Objective data sheet Rev. 2 — 30 October 2020 24 / 98 Table 12. Slave timing values Specifications Label Description Min. Max. Unit fSCLK SCLK frequency 0 4 MHz tSCLK SCLK Period 250 — ns tSCLKH SCLK high time 100 — ns tSCLKL SCLK low time 100 — ns tHZ Hold time for SPI_MISO signal (transition back to high-z state) — 15 ns tSCS Setup time for SPI_CS_B signal 125 — ns tHCS Hold time for SPI_CS_B signal 240 — ns tWCS Inactive time for SPI_CS_B signal 600 — ns tSET Data setup time for SPI_MOSI signal 10 — ns tHOLD Data hold time for SPI_MOSI signal 10 — ns tDDLY Setup time for SPI_MISO signal (transition out of high-z state) — 50 ns SPI_CS_B tSCS SCLK tSET SPI_MOSI SPI_MISO tHOLD tSCLK tSCLKH tSCLKL tDDLY tHCS tWCS High-Impedance tHZ High-Impedance Figure 18. SPI timing diagram (4-wire mode) 11.6 SPI timing specifications (software enabled 3-wire mode) Table 13 and Figure 19 specify and illustrate the minimum and maximum timing parameter values for correct SPI interface functionality when FXLS8964AF is operated in 3-wire (software enabled) SPI mode. FXLS8964AF only supports SPI mode '00', corresponding to CPOL = 0, and CPHA = 0. In this mode, the active state of the clock is high and the idle state is low. Data is latched on the rising edge of the clock and propagated on the falling edge. All timing specifications shown in Table 13 were determined under the following conditions: 10 pF capacitor and 1 kΩ pull-up resistor present on all SPI signals, 105 °C, 1.8 V. |
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