FXLS8964AF datasheet(67/98 Pages) NXP

67 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2 — 30 October 2020

67 / 98

mode change when transitioning from WAKE-to-SLEEP or SLEEP-to-WAKE with

BUF_CONFIG1[BUF_GATE] = 0. The buffer contents are also automatically flushed on a

transition from STANDBY to ACTIVE or STANDBY to EXT_TRIG mode. The buffer may

be prevented from being flushed when transitioning from WAKE-to-SLEEP or SLEEP-to-

WAKE by setting

BUF_CONFIG1[BUF_GATE] = 1.

Disabling the buffer will clear the

BUF_STATUS[BUF_OVF] and

BUF_STATUS[BUF_WMRK] event flags. Disabling the buffer also clears the

BUF_STATUS[BUF_CNT] field. The SYS_MODE[BUF_GATE_ERR] and

SYS_MODE[buf_gate_cnt] fields are also reset when the buffer is disabled, flushed, or

the entire contents are read out by the host.

Notes for using triggered operating mode with Auto-WAKE/SLEEP mode enabled:

1. When BUF_MODE = 11b,

ASLP_COUNT ≥ 1, and the ACTIVE bit is set,

FXLS8964AF will immediately enter the WAKE mode. After

ASLP_COUNT ODR

periods, the buffer is flushed and the part will enter SLEEP mode. The buffer will

collect up to

BUF_CONFIG2[BUF_WMRK] samples at the SLEEP mode ODR before

the trigger event occurs (in stream mode).

2. After the trigger event, FXLS8964AF will enter WAKE mode and remain there

regardless of the setting made in

ASLP_COUNT, ignore any subsequent triggers, and

collects (32 - BUF_WMRK[5:0]) samples at the WAKE mode ODR, set the BUF_OVF

flag, and cease collecting more data until the host flushes the buffer or reads out

all of the contents. Once the buffer is emptied or flushed, the triggered mode is re-

armed, but FXLS8964AF must first re-enter SLEEP mode (which will happen after

ASLP_COUNT WAKE ODR periods) before a second set of data can be collected.

3. The

BUF_CONFIG1[BUF_GATE] setting is ignored and has no effect. The buffer

contents are automatically flushed when FXLS8964AF transitions from WAKE to

SLEEP.

4. The interrupt events that prevent FXLS8964AF from entering SLEEP mode will also

prevent the operation of the triggered mode (which requires FXLS8964AF to first enter

the SLEEP mode).

13.25 BUF_CONFIG2 register (address 27h)

Table 79. BUF_CONFIG2 register (address 27h) bit allocation

Bit

Name

BUF_

FLUSH

WAKE_

SRC_BUF

BUF_WMRK[5:0]

Reset

Access

R/W

Table 80. BUF_CONFIG2 register (address 27h) bit description

Field

Description

BUF_FLUSH

Buffer flush enable:

0: No pending buffer flush operation, or buffer flush completed

1: Buffer flush enable: all buffer contents and related event flags are cleared. The

SYS_

MODE[BUF_GATE_ERR] and SYS_MODE[BUF_GATE_CNT[4:0]] fields are also cleared.

The BUF_FLUSH bit is self-cleared within one internal clock cycle, and as such will not be observable

in a logic high state through the I2C or SPI interfaces.

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