FXLS8964AF datasheet(37/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

37 / 98

13.1 INT_STATUS register (address 00h)

Table 20. INT_STATUS register (address 00h) bit allocation

Bit

Name

SRC_DRDY SRC_OVF

SRC_BUF

SRC_

SDCD_OT

SRC_

SDCD_WT

SRC_

ORIENT

SRC_ASLP SRC_BOOT

Reset

Access

Table 21. INT_STATUS register (address 00h) bit description

Field

Description

SRC_DRDY

Output data-ready event flag

0: A new set of XYZ acceleration and temperature data is not available.

1: A new set of XYZ acceleration and temperature data is available

Notes:

• The SRC_DRDY flag is cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are

read.

• Whenever BUF_CONFIG1[BUF_MODE1:0]] > 00b (buffer enabled), SRC_DRDY is held at logic

'0'.

• When BT_MODE=GND, SRC_DRDY bit and the signalled interrupt is cleared whenever one or

more of the VECM, and OUT_X/Y/Z registers are read.

• When BT_MODE=VDD, SRC_DRDY bit is cleared whenever one or more of the VECM, and

OUT_X/Y/Z registers are read. However the data ready interrupt is signalled for TPULSE-MOT

seconds (5 ms typ) and it clears itself automatically. The current data ready interrupt pulse will be

terminated when the device is transitioned into STANDBY mode before its completion and thus

may not span for entire TPULSE-MOT seconds.

SRC_OVF

Output data overflow event flag

0: No overflow condition detected.

1: A new set of XYZ acceleration and temperature output data was latched into

OUT_X/Y/Z and

TEMP_OUT registers before the previous set was completely read by the host.

Notes:

• SRC_OVF will not be set if at least one of the OUT_X/Y/Z registers was read before the new data

set arrives.

• Whenever the INT_STATUS register is read, SRC_OVF is cleared.

• Whenever BUF_CONFIG1[BUF_MODE[1:0]] > 00b (buffer enabled), SRC_OVF is held at logic '0'.

SRC_BUF

Output data buffer status event flag

0: No output buffer event status flags are active

1: One or more output buffer status event flags are active (BUF_WMRK | BUF_OVF |

BUF_GATE_ERR); reading the

BUF_STATUS register will provide more information on the

BUF_WMRK or BUF_OVF event flag(s) that are currently active. Reading the

SYS_MODE register

will provide information on the BUF_GATE_ERR flag status.

Notes:

• The SRC_BUF flag will only be active when BUF_CONFIG1[BUF_MODE[1:0]] > 00b.

• The BUF_WMRK event flag will not participate in SRC_BUF interrupt generation in triggered mode

(the BUF_WMRK flag will be asserted after the buffer is triggered, but it will not signal an external

interrupt as with the other buffer operating modes). If it is required to know when the trigger event

has taken place, the host may use the SDCD or ORIENT interrupts, as appropriate, to indicate

when the buffer is triggered. When the buffer is full, the SRC_BUF flag will be set and an external

interrupt will be signaled on the INT1 or INT2 pins, if configured.

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