FXLS8964AF datasheet(50/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

50 / 98

Field

Description

6:5

ST_AXIS_SEL[1:0]

Self-test axis selection

This bit field selects the transducer axis to test using the Self-Test function. The ST_POL bit allows

either positive or negative self-test displacements to be applied.

The host system may use the self-test function to verify the functionality of both the transducer and

signal measurement chain without the need to apply an external acceleration stimulus.

Notes:

• The data output from the two axes that are not selected by ST_AXIS_SEL during the self-test

sequence are not meaningful and should be ignored.

• It is recommended to minimize the communication traffic on the device serial interface during the

measurement phase in order to reduce the susceptibility of the self-test response signal to induced

noise. Hence, it is strictly recommended to operate Self-test in interrupt mode.

00b: (default): Self-test function is disabled

01b: Self-test function is enabled for X-axis

10b: Self-test function is enabled for Y-axis

11b: Self-test function is enabled for Z-axis

ST_POL

Self-test displacement polarity

0 (default): Proof mass displacement for the selected axis is in the positive direction.

1: Proof mass displacement for the selected axis is in the negative direction.

SPI_M

SPI interface mode selection; selects between 3- and 4-wire operating modes for the SPI interface:

0 (default): 4-wire interface mode is selected

1: 3-wire interface mode is selected

Notes:

• The state of this bit is only relevant when the SPI interface mode is selected (INTF_SEL = VDD).

• When INTF_SEL = VDD and SPI_M = 1, the SDA/SPI_MOSI pin becomes the bi-directional

SPI_DATA pin; the SA0/MISO pin is unused and placed in a high-impedance state.

• 4-wire mode is selected by default after a POR/BOR event or when exiting Hibernate mode.

• If INTF_SEL = VDD and the SPI_MOSI and SPI_MISO lines are directly connected together on the

PCB, 3-wire SPI mode is enabled regardless of the setting of this bit

2:1

FSR[1:0]

Full-scale measurement range (FSR) selection

00b: ±2 g; 0.98 mg/LSB (1024 LSB/g) nominal sensitivity

01b (default): ±4 g; 1.95 mg/LSB (512 LSB/g) nominal sensitivity

10b: ±8 g; 3.91 mg/LSB (256 LSB/g) nominal sensitivity

11b: ±16 g; 7.81 mg/LSB (128 LSB/g) nominal sensitivity

ACTIVE

Standby/Active mode selection

This bit selects between Standby mode and Active mode.

Note:

• When INT2_FUNC = 1, the Active bit becomes read only via the I2C or SPI interface as the INT2

pin logic state directly controls the device operating mode. The INT2_FUNC may only be enabled

(set to 1) when ACTIVE = 0. Similarly, the ACTIVE bit may only be set if INT2_FUNC = 0.

0: FXLS8964AF is placed in Standby mode and draws the minimum amount of current on the VDD pin

(IDD-STBY). This is the default mode after a POR or soft reset event.

1: FXLS8964AF is placed in Active mode and draws an IDD corresponding to the selected ODR in

HPM, the selected ODR in LPM, or the user-selected decimation and idle time settings in FPM.

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