FXLS8964AF datasheet(58/98 Pages) NXP

58 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2 — 30 October 2020

58 / 98

Field

Description

HIBERNATE_EN

Hibernate mode enable:

0: Hibernate mode not enabled; device is operating per the mode selected in WAKE_PM/SLEEP_

PM[1:0]

1: Commands device to enter Hibernate mode; all RAM register contents will be lost.

Notes:

When BT_MODE = GND:

When Hibernate Mode is selected, FXLS8964AF is completely shut down (similar to removing the

VDD supply), with all register contents lost. To exit Hibernate Mode, a positive or negative going edge

must be applied to the SPI_CS_B/WAKE_UP pin (logic level must toggle from the state applied at

the time this bit was set). The host must then wait TBOOT1 ms for the part to re-enter Standby mode

before attempting communications over the I2C or SPI interfaces.

When BT_MODE = VDD:

Hibernate mode is automatically entered/exited based on the level input to the MOT_DET pin. The

part will directly enter Active mode with the preconfigured motion detection settings when MOT_DET

is pulled high. The host must wait TBOOT2 ms for the for the boot process to complete and the

motion detection process to begin. When MOT_DET is brought low, the part will automatically enter

Hibernate mode to conserve power.

13.16 WAKE_IDLE_LSB register (address 1Ah)

This register, along with WAKE_IDLE_MSB, sets the unsigned 12-bit WAKE mode idle

time (off time).

Note: The contents of this register are only meaningful when

SENS_CONFIG2[WAKE_PM[1:0]] = 1xb.

The counter period is nominally 312.5 µs/LSB, providing a range of 312.5 µs to 1.28

seconds. The idle time + measurement time (set by the WAKE mode decimation factor)

forms the measurement period (ODR–1) as described in the Section 13.13 register

description.

Table 60. WAKE_IDLE_LSB register (address 1Ah) bit allocation

Bit

Name

WAKE_IDLE[7:0]

Reset

Access

R/W

13.17 WAKE_IDLE_MSB register (address 1Bh)

Flexible Power Mode WAKE idle time MSB. The contents of this register are only

meaningful when

SENS_CONFIG2[WAKE_PM[1:0]] = 1xb.

Table 61. WAKE_IDLE_MSB register (address 1Bh) bit allocation

Bit

Name

WAKE_IDLE[11:8]

Reset

Access

R/W

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