NTP53X2 datasheet(107/133 Pages) NXP

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NXP Semiconductors

NTP53x2

NTAG 5 link - NFC Forum-compliant I2C bridge

NTP53x2

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Product data sheet

Rev. 3.3 — 3 July 2020

COMPANY PUBLIC

544533

107 / 133

8.4.6 SRAM PHDC Mode

This mode is similar to SRAM mirror mode. This mode needs to be enabled, when PHDC

communication scheme as defined in NFC Forum PHDC specification shall be used.

NFC will always get a response when accessing SRAM.

8.5 Energy harvesting

NTAG 5 link provides the capability to supply external low-power devices with energy

harvested from the NFC field of an NFC device.

When DISABLE_POWER_CHECK bit is set to 0b, minimum provided output power can

be configured by setting desired voltage and minimum required output current in the

related configuration bytes (see Section 8.1.3.18).

WARNING: Sufficient RF field is required when DISABLE_ POWER_CHECK is

set to 0b to have access to EEPROM. As long as NTAG 5 link detects too less

energy to be harvested from the field only INVENTORY command and READ/WRITE

CONFIGURATION to access session registers will be handled. This feature ensures

a stable system, as the host will only be supplied if there is sufficient energy available.

However, during design phase we recommend disabling this power check.

The provided output power in general of course depends on many parameters like the

strength of the NFC field, the antenna size, or the distance from the NFC device. The

design ensures with the right settings, that VOUT is only enabled, when sufficient energy

can be harvested from the NFC field.

1.8 V, 2.4 V or 3 V output voltage can be selected by coding EH_VOUT_V_SEL

accordingly.

Minimum required load current can be coded in EH_VOUT_I_SEL configuration field.

VOUT and VCC need to be connected as soon as energy harvesting is used. Otherwise

there is no EEPROM access possible from NFC perspective and status registers may

contain invalid information.

Appropriate capacitor dependent on load needs to be placed between VOUT and ground

to close energy gaps during miller pauses. An example circuit is illustrated in the figure

below.

VOUT pin shall be kept floating (not connected) in case energy harvesting feature is not

used. If energy harvesting is disabled, pin will be connected to GND internally.

With EH_ENABLE configuration bit st to 1b, energy harvesting will be enabled after boot,

automatically and all energy harvesting-related session register bits are meaningless.

When enabling energy harvesting via session registers, EH_MODE, EH_VOUT_SEL

and EH_IOUT_SEL needs to be configured properly in the related configuration bytes.

EH_ENABLE configuration bit need to be 0b in this case.

After boot, session registers can be used to first trigger current detection by setting

EH_TRIGGER to 1b, then poll for EH_LOAD_OK that gets 1b and finally set

EH_TRIGGER and EH_ENABLE to 1b, or directly enable energy harvesting by setting

EH_TRIGGER and EH_ENABLE bit to 1b (see Table 97).

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