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NTP53X2 bảng dữ liệu(PDF) 56 Page - NXP Semiconductors |
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NTP53X2 bảng dữ liệu(HTML) 56 Page - NXP Semiconductors |
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56 / 133 page  NXP Semiconductors NTP53x2 NTAG 5 link - NFC Forum-compliant I2C bridge NTP53x2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 3.3 — 3 July 2020 COMPANY PUBLIC 544533 56 / 133 Table 99. I2C Slave Configuration Definition (I2C_SLAVE_ADDR_REG) Access Bit Name NFC I2C Value Description 7 RFU R R 0b 6 to 0 I22_SLAVE_ADDR R R 54h I2C slave address used in slave configuration Table 100. I2C Slave Configuration Definition (I2C_SLAVE_CONFIG_REG) Access Bit Name NFC I2C Value Description 7 to 5 RFU R R 000b 0b WDTdid not expire in previous transaction 4 I2C_WDT_EXPIRED R R 1b Previous transaction was not successful. WDT expired. This bit gets cleared automatically, when new transaction is triggered. 3 I2C_SOFT_RESET R/W R/W 0b Setting this bit to 1b, resets the I2C state machine and relases th SCL/ SDA lines. This bit gets cleared automatically. 0b Slave does not reset if repeated start is received (Default) 2 I2C_S_REPEATED_ START R R/W 1b I2C slave resets internal state machine on repeated start 1 RFU R R 0b 0b I2C interface enabled (default) 0 DISABLE_I2C (see Section 8.3.1.1.6) R/W R 1b I2C interface disabled 8.1.4.10 System reset generation System reset can be generated by both the interfaces by writing to RESET_GEN_REG register using WRITE CONFIG command (see Section 8.2.3.2.2). Writing E7h will trigger the system reset. This byte gets automatically reset after the system reset. Table 101. RESET_GEN_REG location Block Address NFC I2C Byte 0 Byte 1 Byte 2 Byte 3 AAh 10AAh RESET_GEN_REG RFU 8.1.4.11 Clear event detection register Event detection pin is cleared i.e. released when writing 01h to the Clear Event Detection Register from NFC or I2C interface. The bit gets cleared after releasing the ED pin automatically. Other values are RFU. |
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