NTP53X2 datasheet(35/133 Pages) NXP

35 / 133 page

NXP Semiconductors

NTP53x2

NTAG 5 link - NFC Forum-compliant I2C bridge

NTP53x2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.3 — 3 July 2020

COMPANY PUBLIC

544533

35 / 133

8.1.3.16 Pulse Width Modulation duty cycle settings

Details can be found in PWM Mode section (see Section 8.3.4).

Table 45. Pulse Width Modulation Duty Cycle Configuration Location (PWMx_ON and PWMx_OFF)

Block Address

NFC

I2C

Byte 0

Byte 1

Byte 2

Byte 3

3Ah

103Ah

PWM0_ON (LSB)

PWM0_ON (MSB)

PWM0_OFF (LSB)

PWM0_OFF (MSB)

3Bh

103Bh

PWM1_ON (LSB)

PWM1_ON (MSB)

PWM1_OFF (LSB)

PWM1_OFF (MSB)

Table 46. Pulse Width Modulation Duty Cycle Session Register Location (PWMx_ON and PWMx_OFF)

Block Address

NFC

I2C

Byte 0

Byte 1

Byte 2

Byte 3

A4h

10A4h

PWM0_ON_

REG (LSB)

PWM0_ON_

REG (MSB)

PWM0_OFF_REG (LSB)

PWM0_OFF_

REG (MSB)

A5h

10A5h

PWM1_ON_

REG (LSB)

PWM1_ON_

REG (MSB)

PWM1_OFF_REG (LSB)

PWM1_OFF_

REG (MSB)

Table 47. Pulse Width Modulatin ON time Configuration Definition (PWMx_ON and PWMx_ON_REG)

Bit

Name

Default

Value

Description

7 to 4

RFU

all 0b

3 to 0

PWMx_ON (MSB)

all 0b

7 to 0

PWMx_ON (LSB)

all 0b

coded time PWM channel x output will be asserted HIGH

Table 48. Pulse Width Modulation OFF time Configuration Definition (PWMx_OFF and PWMx_OFF_REG)

Bit

Name

Default

Value

Description

7 to 4

RFU

all 0b

3 to 0

PWMx_OFF (MSB)

all 0b

7 to 0

PWMx_OFF (LSB)

all 0b

coded time PWM channel x output will be asserted LOW

PWM on and off times are coded by using maximum 12 bits. To code for example,

PWM0_ON as 0123h, PWM0_ON (LSB) is set to 23h, and PWM0_ON (MSB) is set to

01h.

8.1.3.17 Watch Dog Timer settings

I2C Watch Dog Timer settings can be adjusted and enabled via configuration bytes from

both interfaces. Related session registers are read only. Watch Dog Timer 16-bit default

value is 0848h. Details can be found in WDT section (see Section 8.3.1.3).

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