VSC7511 datasheet(153/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

138

The rewriter updates a frame’s FCS when required or instructed to do so. Different handling is available

for frames injected by the CPU and for all other frames.

For non-CPU injected frames, the following update options are available:

•

Never update the FCS.

•

Conditional update: Update the FCS if the frame was modified due to PTP time stamping, VLAN

tagging, or DSCP remarking.

•

Always update the FCS.

In addition, the rewriter can update the FCS for all frames injected from the CPU through the CPU

injection queues in the CPU port module:

•

Never update the FCS.

•

Always update the FCS.

3.13.4

PTP Time Stamping

The following table lists the registers associated with PTP time stamping.

The rewriter can do various different PTP time stamping in the egress frame:

Residence time. Adds the frame’s residence time through the switch to the PTP correction field (byte-

offset 8).

Add/subtract. Adds the frame’s Tx time to the correction field (byte-offset 8) or subtract the frame’s Rx

time from the correction field.

Time-of-day. Samples and writes the 80-bit time-of-day into the PTP origin time stamp (byte-offset 34).

Set reserved bytes. Writes the RxTime into the PTP reserved bytes (byte-offset 16).

Clear reserved bytes. Writes zero into the PTP reserved bytes (byte-offset 16).

This can be done for PTP frames over IEEE802.3/Ethernet, PTP frames over UDP over IPv4, and PTP

frames over UDP over IPv6. In addition, frames can be VLAN tagged. The rewriter automatically finds the

correct location of the PTP header in the frame.

The rewriter takes the following frame properties from the analyzer as input.

•

IS2 rewriter action (IS2_ACTION.REW_OP[2:0]), which can be either one-step, two-step, or origin.

•

The frame’s Rx time stamp, adjusted for I/O path delays and ingress delays according to ingress

actions.

•

IS2 rewriter actions for one-step PTP: Add/subtract mode, egress delay adjustment.

•

Ingress backplane mode ANA:PORT:PTP_CFG.PTP_BACKPLANE_MODE from the frame’s

ingress port.

In addition, the following egress port properties are used.

•

Egress port delay (REW:PORT:PTP_DLY1_CFG).

•

Egress backplane mode (REW:PORT:PTP_CFG.PTP_BACKPLANE_MODE).

PORT_CFG.FCS_UPDATE_CPU_ENA

FCS update configuration for CPU

injected frames.

Per port

Table 109 •

PTP Time Stamping Registers

Description

Replication

REW:PORT:PTP_CFG

PTP Configuration of egress port

Per port

REW:PORT:PTP_DLY1_CFG

Egress delay configuration

Per port

Table 108 •

FCS Updating Registers (continued)

Description

Replication

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