VSC7511 datasheet(32/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

3.1.1

Supported SerDes Interfaces

The device support a range of SerDes interfaces. The following table lists the SerDes interfaces

supported by the SerDes ports, including standards, data rates, connectors, medium, and coding for

each interface.

3.1.2

PCIe Mode

SerDes macro SERDES6G_2 can either be used as a standard Ethernet interface or as a PCIe interface.

This is controlled in HSIO::HW_CFG.PCIE_ENA. When PCIe is enabled, port 10 cannot be used in

option 0 as the SerDes is occupied by the PCIe.

3.1.3

Logical Port Numbers

The analyzer and the rewriter uses in many places a logical port number. For instance, when link

aggregation is enabled, all ports within a link aggregation group must be configured to use the physical

port number of the port with the lowest port number within the group as logical port group ID. The

mapping to a logical port number is configured in ANA:PORT:PORT_CFG.PORTID_VAL.

3.2

Port Modules

All port modules contain a MAC. Ports connecting to a high-speed I/O SerDes macro also contain a PCS.

3.2.1

MAC

This section provides information about the high-level functionality and the configuration options of the

Media Access Controller (MAC) that is used in each of the port modules.

The MAC supports the following speeds and duplex modes:

•

SERDES1G ports: 10/100/1000 Mbps in full-duplex mode and 10/100 Mbps in half-duplex mode

•

SERDES6G ports: 10/100/1000/2500 Mbps in full-duplex mode and 10/100 Mbps in half-duplex

mode.

The following table lists the registers associated with configuring the MAC.

Table 5 •

Supported SerDes Interfaces

Port Interface Specification

Port Speed Data Rate

Connector Medium

Coding

100BASE-FX

IEEE 802.3, Clause 24 100M

125 Mbps

SFP

PCB

4B5B

x x

SGMII

Cisco

1.25 Gbps

PCB

8B10B

x x

SFP

SFP-MSA

1.25 Gbps

SFP

PCB

8B10B

x x

1000BASE-KX IEEE802.3, Clause 70 1G

1.25 Gbps

PCB,

backplane

8B10B

x x

2.5G

Proprietary (aligned to

SFP)

2.5G

3.125 Gbps

PCB

8B10B

Table 6 •

MAC Configuration Registers

Description

Replication

DEV::CLOCK_CFG

Reset and speed configuration

Per port

DEV::MAC_ENA_CFG

Enabling of Rx and Tx data paths

Per port

DEV::MAC_MODE_CFG

Port mode configuration

Per port

DEV::MAC_MAXLEN_CFG

Maximum length configuration

Per port

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