VSC7511 datasheet(57/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

(PHY_CTRL_EXT3.ACTIPHY_SLEEP_TIMER). The actual sleep time duration is random, from –80 ms

to 60 ms, to avoid two linked PHYs in ActiPHY mode entering a lock-up state during operation.

After sending signal energy on the relevant media, the PHY returns to the low power state.

3.5.6.2

Link Partner Wake-up State

In the link partner wake-up state, the PHY attempts to wake up the link partner. Up to three complete FLP

bursts are sent on alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer,

which is set using register bits 20E1.12:11.

After sending signal energy on the relevant media, the PHY returns to the low power state.

3.5.6.3

Normal Operating State

In normal operation, the PHY establishes a link with a link partner. When the media is unplugged or the

link partner is powered down, the PHY waits for the duration of the programmable link status time-out

timer, which is set using ACTIPHY_LINK_TIMER_MSB_CFG and ACTIPHY_LINK_TIMER_LSB_CFG in

the PHY_AUX_CTRL_STAT register. It then enters the low power state.

3.5.7

Testing Features

The integrated transceivers include several testing features designed to facilitate performing system-

level debugging.

3.5.7.1

Ethernet Packet Generator (EPG)

The Ethernet Packet Generator (EPG) can be used at each of the 10/100/1000BASE-T speed settings

for copper Cat5 media to isolate problems between the MAC and the PHY, or between a local PHY and

its remote link partner. Enabling the EPG feature effectively disables all MAC interface transmit pins and

selects the EPG as the source for all data transmitted onto the twisted pair interface.

Important The EPG is intended for use with laboratory or in-system testing equipment only. Do not use

the EPG testing feature when the PHY is connected to a live network.

To use the EPG feature, set PHY_1000BT_EPG2.EPG_ENA to 1.

When PHY_1000BT_EPG2.EPG_RUN_ENA is set to 1, the PHY begins transmitting Ethernet packets

based on the settings in the PHY_1000BT_EPG1 and PHY_1000BT_EPG2 registers. These registers

set:

•

Source and destination addresses for each packet

•

Packet size

•

Inter-packet gap

•

FCS state

•

Transmit duration

•

Payload pattern

If PHY_1000BT_EPG1.TRANSMIT_DURATION_CFG is set to 0, PHY_1000BT_EPG1.EPG_RUN_ENA

is cleared automatically after 30,000,000 packets are transmitted.

3.5.7.2

CRC Counters

Two separate CRC counters are available in the PHY: a 14-bit good CRC counter available through

PHY_CRC_GOOD_CNT.CRC_GOOD_PKT_CNT and a separate 8-bit bad CRC counter in

PHY_CTRL_EXT4.CRC_1000BT_CNT.

3.5.7.3

Far-End Loopback

The far-end loopback testing feature is enabled by setting

PHY_CTRL_EXT1.FAR_END_LOOPBACK_ENA to 1. When enabled, it forces incoming data from a link

partner on the current media interface, into the MAC interface of the PHY, to be re-transmitted back to the

link partner on the media interface as shown in the following illustration. The incoming data also appears

on the receive data pins of the MAC interface. Data present on the transmit data pins of the MAC

interface is ignored when using this testing feature.

Note: The far-end loopback is only operational in 1Gbps mode.

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