VSC7511 datasheet(30/324 Pages) MICROSEMI

30 / 324 page

Product Overview

VMDS-10488 VSC7511 Datasheet Revision 4.2

Synchronous Ethernet allows for the transfer of network timing from one reference to all network

elements. In the device, each port can recover its ingress clock and output the recovered clock to one of

up to two recovered clock output pins. External circuitry can then generate a stable reference clock input

used for egress and core logic timing in the device.

The Precision Time Protocol (PTP) allows for the network-wide synchronization of precise time of day. It

is also possible to derive network timing. PTP can operate with a one-step clock or a two-step clock. For

one-step clocks, a frame’s residence time is calculated and stamped into the frame at departure. For two-

step clocks, a frame’s residence time is simply recorded and provided to the CPU for further processing.

The CPU can then initiate a follow-up message with the recorded timing.

PTP is supported for a range of encapsulations including PTP over Ethernet/IEEE 802.3 and PTP over

UDP over IPv4/IPv6.

2.3.10

CPU System and Interfaces

The device contains a fast 250 MHz 8051 and a high bandwidth Ethernet Frame DMA engine.

The device supports external CPU register access through the on-chip PCIe 1.x endpoint controller,

through specially formatted Ethernet frames on the NPI port (Microsemi’s Versatile Register Access

Protocol), or through register access interface using SPI protocol. External CPUs can inject or extract

Ethernet frames through NPI port, through PCIe DMA access, or through register read/writes (using any

VSC7511 bảng dữ liệu(PDF) 30 Page - Microsemi Corporation