VSC7511 datasheet(178/324 Pages) MICROSEMI

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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

163

Figure 57 •

Chip Registers Memory Map

The registers in the 0x70000000 through 0x70FFFFFF region are physically located inside the VCore-Ie

system, so read and write access to these registers is fast (done in a few clock cycles). All registers in

this region are considered fast registers.

Registers in the 0x71000000 through 0x71FFFFFF region are located inside the switch core; access to

registers in this range takes approximately 1 µs. The DEVCPU_ORG and DEVCPU_QS targets are

special; registers inside these two targets are faster; access to these two targets takes approximately

0.1 µs. Registers located inside the switch core are not accessible through PCIe interface.

When more than one CPU is accessing registers, the access time may be increased. For more

information, see Register Access and Multimaster Systems.

Writes to the Chip Registers region is buffered (there is a one-word write buffer). Multiple back-to-back

write access pauses the shared bus until the write buffer is freed up (until the previous write is done). A

read access pause the shared bus until read data is available. Executing a write immediately followed by

a read requires the write to be done before the read can be started.

4.3.3

SI Flash Region

Read access from the SI Flash region initiates Flash formatted read access on the SI pins of the device

by means of the SI boot controller.

The SI Flash region cannot be written to. Writing to the SI interface must be implemented by using the SI

master controller. For more information, see SI Master Controller, page 193. For legacy reasons, it is also

possible to write to the SI interface by using the SI boot master’s software “bit-banging” register interface.

For more information, see SI Boot Controller, page 191.

4.3.4

PCIe Region

Read and write access from or to the PCIe region maps to outbound read and write access on the PCIe

interface of the device by means of the PCIe endpoint controller. For more information about the PCIe

endpoint controller and how to reach addresses in 32-bit and 64-bit PCIe environments, see PCIe

Endpoint Controller.

VCore Registers

UART Registers

TWI Registers

0x70100000

0x70100400

0x70100800

1 MB

1 KB

0x70000000

SBA Registers

0x70110000

0x70110400

1 KB

Reserved

59 KB

Reserved

1 KB

0x70101400

SIMC Registers

1 KB

0x70101000

Reserved

3 KB

UART2 Registers

1 KB

0x70100C00

Switch Core Registers

0x71000000

0x72000000

16 MB

PCIe Registers

0x70111000

0x70112000

1 KB

Reserved

15 MB

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