AT90LS8535-4AI datasheet(26/127 Pages) ATMEL

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AT90S/LS8535

1041H–11/01

sponding interrupt of External Interrupt Request 0 is executed from program memory

address $001. See also “External Interrupts.”

• Bits 5.0 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read as zero.

General Interrupt Flag

• Bit 7 – INTF1: External Interrupt Flag1

When an edge or logical change on the INT1 pin triggers an interrupt request, INTF1

becomes set (one). This flag is always cleared (0) when the pin is configured for low-

level interrupts, as the state of a low-level interrupt can be determined by reading the

PIN register.

If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the

interrupt address $002. For edge and logic change interrupts, this flag is cleared when

the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logi-

cal “1” to it.

• Bit 6 – INTF0: External Interrupt Flag0

When an edge or logical change on the INT0 pin triggers an interrupt request, INTF0

becomes set (one). This flag is always cleared (0) when the pin is configured for low-

level interrupts, as the state of a low-level interrupt can be determined by reading the

PIN register.

If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the

interrupt address $001. For edge and logic change interrupts, this flag is cleared when

the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logi-

cal “1” to it.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read as zero.

Timer/Counter Interrupt Mask

• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at

vector $003) is executed if a compare match in Timer/Counter2 occurs (i.e., when the

OCF2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector

$004) is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set

in the Timer/Counter Interrupt Flag Register [TIFR]).

Bit

$3A ($5A)

INTF1

INTF0

––

–

GIFR

Read/Write

R/W

Initial Value

Bit

$39 ($59)

OCIE2

TOIE2

TICIE1

OCIE1A

OCIE1B

TOIE1

–

TOIE0

TIMSK

Read/Write

R/W

Initial Value

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