AT90LS8535-4AI datasheet(24/127 Pages) ATMEL

24 / 127 page

AT90S/LS8535

1041H–11/01

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period

TOUT. Refer to page 49 for details on operation of the Watchdog.

Figure 27. Watchdog Reset during Operation

MCU Status Register –

MCUSR

The MCU Status Register provides information on which reset source caused an MCU

reset.

• Bits 7..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read as zero.

• Bit 1 – EXTRF: External Reset Flag

After a power-on reset, this bit is undefined (X). It can only be set by an External Reset.

A Watchdog Reset will leave this bit unchanged. The bit is cleared by writing a logical

zero to the bit.

• Bit 0 – PORF: Power-on Reset Flag

This bit is only set by a Power-on Reset. A Watchdog Reset or an External Reset will

leave this bit unchanged. The bit is cleared by writing a logical zero to the bit.

To summarize, Table 5 shows the value of these two bits after the three modes of reset.

To make use of these bits to identify a reset condition, the user software should clear

both the PORF and EXTRF bits as early as possible in the program. Checking the

PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before

an External or Watchdog Reset occurs, the source of reset can be found by using Table

Bit

543210

$34 ($54)

––

––––

EXTRF

PORF

MCUSR

Read/Write

RRRRR

R/W

Initial Value

0000

See Bit Description

Table 5. PORF and EXTRF Values after Reset

Reset Source

EXTRF

PORF

Power-on Reset

Undefined

External Reset

Unchanged

Watchdog Reset

Unchanged

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