AT90LS8535-4AI datasheet(15/127 Pages) ATMEL

15 / 127 page

AT90S/LS8535

1041H–11/01

Indirect Program Addressing,

IJMP and ICALL

Figure 18. Indirect Program Memory Addressing

Program execution continues at address contained by the Z-register (i.e., the PC is

loaded with the contents of the Z-register).

Relative Program Addressing,

RJMP and RCALL

Figure 19. Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k is from -

2048 to 2047.

EEPROM Data Memory

The AT90S8535 contains 512 bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM

and the CPU is described on page 51 specifying the EEPROM address registers, the

EEPROM data register and the EEPROM control register.

For the SPI data downloading, see page 99 for a detailed description.

Memory Access Times

and Instruction

Execution Timing

This section describes the general access timing concepts for instruction execution and

internal memory access.

The AVR CPU is driven by the System Clock Ø, directly generated from the external

clock crystal for the chip. No internal clock division is used.

Figure 20 shows the parallel instruction fetches and instruction executions enabled by

the Harvard architecture and the fast-access register file concept. This is the basic pipe-

lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks and functions per power-unit.

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