82801E datasheet(55/84 Pages) INTEL

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Intel® 82801E C-ICH

Advance Information Datasheet

3.4.5

Power Planes for Input Signals

Table 33 shows the power plane associated with each input signal, as well as what device drives the

signal at various times. Valid states include:

• High

• Low

• Static: Will be high or low, but will not change

• Driven: Will be high or low, and is allowed to change

• Running: For input clocks

STPCLK#

CPU I/O

PCIRST#

High

SMBus Interface

SMBCLK, SMBDATA

Main I/O

RSMRST#

High-Z

System Management Interface

SMLINK[1:0]

Main I/O

RSMRST#

High-Z

Miscellaneous Signals

SPKR

Main I/O

PCIRST#

High-Z with

internal pull-up

Low

SUSCLK

Main I/O

RSMRST#

Running

Unmuxed GPIO Signals

GPIO[18]

Main I/O

PCIRST#

High

See Note 2

GPIO[19:20]

Main I/O

PCIRST#

High

GPIO[21]

Main I/O

PCIRST#

High

GPIO[22]

Main I/O

PCIRST#

High-Z

GPIO[23]

Main I/O

PCIRST#

Low

GPIO[24]

Main I/O

RSMRST#

High-Z

High

GPIO[25]

Main I/O

RSMRST#

High-Z

High

GPIO[27:28]

Main I/O

RSMRST#

HIgh-Z

High

Table 32. Power Plane and States for Output and I/O Signals (Sheet 3 of 3)

Signal Name

Power Plane

Reset Signal

During Reset

Immediately

after Reset

NOTES:

1. The 82801E C-ICH sets these signals at reset for processor frequency strap.

2. I GPIO[18] will toggle at a frequency of approximately 1 Hz when the 82801E C-ICH comes out of reset

3. CPUPWRGD is an open-drain output that represents a logical AND of the VRMPWRGD and PWROK

signals and, thus, are driven low by 82801E C-ICH when either VRMPWRGD or PWROK are inactive.

During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low

to High-Z.

4. GPIO[24:25, 27:28]: These signals remain tri-stated for up to 110 ms after RSMRST# deassertion. At this

point, they will be driven to their default (High) state.

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