PIFE32251B-R47MS datasheet(76/96 Pages) TI1

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TPS65094

SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Application and Implementation

7.2.2.1.3 Selecting the FETs

This controller is designed to drive two NMOS FETs. Typically, lower RDSON values are better for

improving the overall efficiency of the controller. However, higher gate-charge thresholds result in lower

efficiency, so the two must be balanced for optimal performance. As the RDSON for the low-side FET

decreases, the minimum current limit increases; therefore, ensure selection of the appropriate values for

the FETs, inductor, output capacitors, and current-limit resistor. TI's CSD87331Q3D, CSD87381P, and

CSD87588N devices are recommended for the controllers, depending on the required maximum current.

7.2.2.1.4 Bootstrap Capacitor

To ensure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a

capacitor must be connected between the SWx pins and the respective BOOTx pins. TI recommends

placing ceramic capacitors with the value of 0.1 µF for the controllers. During testing, a 0.1-µF, size 0402,

10-V capacitor is used for the controllers.

TI recommends reserving a small resistor in series with the bootstrap capacitor in case the turnon and

turnoff of the FETs must be slowed to reduce voltage ringing on the switch node, which is a common

practice for controller design.

7.2.2.1.5 Selecting the Input Capacitors

Due to the nature of the switching controller with a pulsating input current, a low-ESR input capacitor is

required for best input-voltage filtering and also for minimizing the interference with other circuits caused

by high input-voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x

pin to handle the transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is

recommended for most applications. To achieve the low-ESR requirement, a ceramic capacitor is

recommended. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be

considered. For better input-voltage filtering, the input capacitor can be increased without any limit.

7.2.2.1.5.1 Setting the Current Limit

The current-limiting resistor value must be chosen based on Equation 1.

NOTE

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VSYS

and PGND pins of the FETs. The preferred capacitors for the controllers are two Murata

GRM21BR61E226ME44: 22 µF, 0805, 25 V, ±20%, or similar capacitors.

PIFE32251B-R47MS bảng dữ liệu(PDF) 76 Page - Texas Instruments