PIFE32251B-R47MS datasheet(37/96 Pages) TI1

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VID

Number of

Steps × 3 µs

VOUT

200 µs

Load and Time

Dependent

VID

Number of Steps × 3 µs

VOUT

TPS65094

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SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Detailed Description

6.3.3.3

DVS

BUCK1–BUCK6 and LDOA1–3 support dynamic voltage scaling (DVS) for maximum system efficiency.

The VR outputs can slew up and down in either 10-mV or 25-mV steps using the 7-bit voltage ID (VID)

defined in Section 5.7, Electrical Characteristics: Buck Controllers, and Section 5.8, Electrical

Characteristics: Synchronous Buck Converters. DVS slew rate is minimum 2.5 mV/µs. To meet the

minimum slew rate, VID progresses to the next code at 3-µs (nom) interval per 10-mV step. When DVS is

active, the VR is forced into PWM mode to ensure the output keeps track of VID code with minimal delay.

Additionally, PGOOD is masked when DVS is in progress. Figure 6-5 shows an example of slew down

and up from one VID to another.

Figure 6-5. DVS Timing Diagram I

As shown in Figure 6-6, if a BUCKx_VID[6:0] is set to 7b000 0000, the output voltage slews down to 0.5 V

first, and then drifts down to 0 V as the SMPS stops switching. Subsequently, if a BUCKx_VID[6:0] is set

to a value (neither 7b000 0000 nor 7b000 0001) when the output voltage is less than 0.5 V, the VR ramps

up to 0.5 V first with soft-start kicking in, then it slews up to the target voltage in the aforementioned slew

rate.

NOTE

A fixed 200 µs of soft-start time is reserved for VOUT to reach 0.5 V. In this case, however,

the SMPS is not forced into PWM mode because it otherwise could cause VOUT to droop

momentarily if VOUT is drifting above 0.5 V for any reason.

Figure 6-6. DVS Timing Diagram II

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