PIFE32251B-R47MS datasheet(50/96 Pages) TI1

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SDA

SCL

Data Valid

Change of Data Allowed

SDA

SCL

START

Condition

STOP

Condition

TPS65094

SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Detailed Description

6.5.1.1

F/S-Mode Protocol

The master initiates data transfer by generating a START condition. The START condition exists when a

high-to-low transition occurs on the SDA line while SCL is high (see Figure 6-13). All I2C-compatible

devices should recognize a START condition.

The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data

condition requires the SDA line to be stable during the entire high period of the clock pulse (see

Figure 6-14). All devices recognize the address sent by the master and compare it to their internal fixed

addresses. Only the slave device with a matching address generates an acknowledge (see Figure 6-15),

by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this

acknowledge, the master identifies that the communication link with a slave has been established.

The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data

from the slave (R/W bit = 1). In either case, the receiver must acknowledge the data sent by the

transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on

which one is the receiver. Any 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge

can continue as long as necessary.

To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line

from low to high while the SCL line is high (see Figure 6-13). This STOP condition releases the bus and

stops the communication link with the addressed slave. All I2C-compatible devices must recognize the

STOP condition. Upon the receipt of a STOP condition, all devices detect that the bus is released, and

they wait for a START condition followed by a matching address.

Figure 6-13. START and STOP Conditions

Figure 6-14. Bit Transfer on the I2C Bus

PIFE32251B-R47MS bảng dữ liệu(PDF) 50 Page - Texas Instruments