PIFE32251B-R47MS datasheet(49/96 Pages) TI1

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TPS65094

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SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Detailed Description

6.4

Device Functional Modes

6.4.1

Off Mode

When power supply at the VSYS pin is less than VSYS_UVLO_5V (5.4-V nominal) + VSYS_UVLO_5V_HYS (0.2-V

nominal), the device is in off mode, where all output rails are disabled. If the supply voltage is greater than

VSYS_UVLO_3V (3.6-V nominal) + VSYS_UVLO_3V_HYS (0.15-V nominal) while it is still less than VSYS_UVLO_5V +

VSYS_UVLO_5V_HYS, then the internal band-gap reference (VREF pin) along with LDO3P3 are enabled and

regulated at target values.

6.4.2

Standby Mode

When power supply at the VSYS pin rises above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS, the device enters

standby mode, where all internal reference and regulators (LDO3P3 and LDO5) are running, and I2C

interface and PMICEN pin are ready to respond. All default registers defined in Section 6.6, Register

Maps, should now have been loaded from one-time programmable (OTP) memory. Quiescent current

consumption in standby mode is specified in Section 5.5, Electrical Characteristics: Total Current

Consumption.

6.4.3

Active Mode

The device proceeds to active mode when any output rail is enabled either through an input pin as

discussed in Section 6.3.5, Power Sequencing and VR Control, or by writing to the EN bits through I2C.

Output regulation voltage can also be changed by writing to the VID bits defined in Section 6.6, Register

Maps.

6.5

Programming

6.5.1

2C Interface

The I2C interface is a 2-wire serial interface developed by NXP™ (formerly Philips Semiconductor) (see

the I2C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line

(SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are

pulled high. All the I2C compatible devices connect to the I2C bus through open-drain I/O pins, DATA and

CLK. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master

is responsible for generating the SCL signal and device addresses. The master also generates specific

conditions that indicate the start and stop of data transfer. A slave device receives and/or transmits data

on the bus under control of the master device.

The TPS65094x device works as a slave and supports the following data transfer modes, as defined in the

I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode

(1 Mbps). The interface adds flexibility to the power supply solution, enabling programming of most

functions to new values depending on the instantaneous application requirements. Register contents are

loaded when VSYS higher than VSYS_UVLO_5V is applied to the TPS65094x device. The I

2C interface is

running from an internal oscillator that is automatically enabled when there is an access to the interface.

The data transfer protocol for standard and fast modes are exactly the same, therefore, they are referred

to as F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is

referred to as H/S-mode.

The TPS65094x device supports 7-bit addressing; however, 10-bit addressing and general call address

are not supported. The default device address is 0x5E.

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