PIFE32251B-R47MS datasheet(58/96 Pages) TI1

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TPS65094

SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Detailed Description

6.6.13 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]

All xx_DIS[1:0] bits automatically set to 00 when the corresponding VR is enabled. Discharge resistance

values listed here are approximate.

Figure 6-31. DISCHCNT1 Register (offset = 40h) [reset = 0101 0101]

Bit

Bit Name

BUCK4_DIS[1]

BUCK4_DIS[0]

BUCK3_DIS[1]

BUCK3_DIS[0]

BUCK2_DIS[1]

BUCK2_DIS[0]

BUCK1_DIS[1]

BUCK1_DIS[0]

TPS65094x

Access

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-24. DISCHCNT1 Register Field Descriptions

Bit

Field

Type Reset

Description

7–6

BUCK4_DIS[1:0]

R/W

BUCK4 discharge resistance

00: No discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

5–4

BUCK3_DIS[1:0]

R/W

BUCK3 discharge resistance

00: No discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

3–2

BUCK2_DIS[1:0]

R/W

BUCK2 discharge resistance

00: No discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

1–0

BUCK1_DIS[1:0]

R/W

BUCK1 discharge resistance

00: No discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

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