DSP56857 datasheet(545/662 Pages) FREESCALE

545 / 662 page

Application:

Date:

Programmer:

Sheet

Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-43

23 of 24

ITCN

Interrupt Control Register (ICTL)

Bits

Name

Description

INT

Interrupt

No interrupt is being presented to the core

An interrupt is being presented to the core

14 - 13

IPLC

Interrupt Priority Level Core

This bit field reflects the state of the new interrupt priority level bits being presented to the core at

the time the last IRQ was taken.

Required nested exception priority levels are 0, 1, 2, or 3

Required nested exception priority levels are 1, 2, or 3

Required nested exception priority levels are 2 or 3

Required nested exception priority level is 3

12 - 6

VAB

Vector Number

This field shows bits [7:1] of the Vector Number of the last IRQ. The field is only updated when the

core jumps to a new interrupt service routine.

INT_DIS

Interrupt Disable

Disables all interrupts

Normal operation (default)

All interrupts disabled

IRQ Control

$1FFF20 + $1A

Bits

15 14 13 12 11 10 9 8 7 6

Read INT

IPLC

VAB

INT_DIS

IRQB_STATE IRQA_STATE

IRQB_EDG IRQA_ EDG

Write

Reset

0 00 000 0

denotes Reserved Bits

See the following page for continuation of this register

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