DSP56857 datasheet(520/662 Pages) FREESCALE

520 / 662 page

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Sheet

5685X Digital Signal Controller User Manual, Rev. 4

B-18

Freescale Semiconductor

denotes Reserved Bits

1 of 3

COP

COP Control Register (COPCTL)

Bits

Name

Description

BYPS

BYPASS (For factory use only)

When this bit is set, it allows factory testing of the COP is accelerated by routing the IPBus clock

to the counter instead of the OSCCLK. This bit should not be set during normal chip operation.

CSEN

COP Stop Enable

This bit controls the operation of the COPcounter Stop mode. It can be changed only when the

CWP bit is set to zero.

CWEN

COP Wait Enable

This bit controls the operation of the COP counter in the Wait mode. It can be changed only when

the CWP bit is set to zero.

CEN

COP Enable

This bit controls the operation of the COP counter. This bit can only be changed when CWP is set

to zero. This bit always reads as zero when the chip is in the Debug mode.

CWP

COP Write Protect

This bit controls the write protection feature of the COP Control (COPCTL) and the COP Timeout

(COPTO) registers. Once set, this bit can only be cleared by resetting the module.

COP Control

$1FFFD0 + $0

Bits

Read

BYPS CSEN CWEN CEN

CWP

Write

Reset

0000

00000

0000

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