DSP56857 datasheet(486/662 Pages) FREESCALE

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5685x Restrictions

5685X Digital Signal Controller User Manual, Rev. 4

17-24

Freescale Semiconductor

17.9 5685x Restrictions

The control afforded by the output enable signals using the BSR and the EXTEST instruction

requires a compatible circuit board test environment to avoid any device-destructive

configurations. Avoid situations when the 5685x output drivers are enabled into actively driven

networks.

During power-up, the TRST pin must be externally asserted to force the TAP Controller into this

state. After power-up is concluded, TMS must be sampled as a Logic 1 for five consecutive TCK

rising edges. If TMS either remains unconnected or is connected to VDD, then the TAP Controller

cannot leave the test-logic-reset state, regardless of the state of TCK.

5685x features a low-power Stop mode invoked using the stop instruction. JTAG interaction with

low-power Stop mode is as follows:

1. The TAP Controller must be in the test-logic-reset state to either enter or remain in Stop

mode. Leaving the TAP Controller test-logic-reset state negates the ability to achieve

low-power, but does not otherwise affect device functionality.

2. The TCK input is not blocked in low-power Stop mode. To consume minimal power, the

TCK input should be tied to ground only.

3. The TMS and TDI pins include On-Chip Pull-Up resistors. In low-power Stop mode, these

two pins should remain either unconnected or connected to VDD to achieve minimal

power consumption.

Because all 5685x clocks are disabled during Stop state, the JTAG interface provides the means

of polling the device status, sampled in the Capture-IR state.

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