DSP56857 datasheet(485/662 Pages) FREESCALE

485 / 662 page

TAP Controller

JTAG Port, Rev. 4

Freescale Semiconductor

17-23

17.8.1.11 Capture Instruction Register (pstate = E)

When the TAP Controller is in this state and a rising edge of TCK occurs, the controller advances

to the Exit1-IR state if TMS is held at a one or the Shift-IR state if TMS is held at a zero.

17.8.1.12 Shift Instruction Register (pstate = A)

In this controller state, the Shift register contained in the Instruction Register (IR) is connected

between TDI and TDO and shifts data one stage towards it’s serial output on each rising edge of

TCK. When the TAP Controller is in this state and a rising edge of TCK occurs, the controller

advances to the Exit1-IR state if TMS is held at a one or remains in the Shift-IR state if TMS is

held at a zero.

17.8.1.13 Exit1 Instruction Register (pstate = 9)

This is a temporary controller state. If TMS is held high, and a rising edge is applied to TCK

while in this state causes the controller to advance to the Update-IR state. This terminates the

scanning process. If TMS is held low and a rising edge of TCK occurs the controller advances to

the Pause-IR state.

17.8.1.14 Pause Instruction Register (pstate = B)

This controller state allows shifting of the Instruction Register (IR) in the serial path between

TDI and TDO to be temporarily halted. All Test Data registers selected by the current instruction

retain their previous state unchanged. The controller remains in this state while TMS is held low.

When TMS goes high and a rising edge is applied to TCK, the controller advances to the

Exit2-IR state.

17.8.1.15 Exit2 Instruction Register (pstate = 8)

This is a temporary controller state. If TMS is held high, and a rising edge is applied to TCK

while in this state, the scanning process terminates and the TAP Controller advances to the

Update-IR state. If TMS is held low and a rising edge of TCK occurs, the controller advances to

the Shift-IR state.

17.8.1.16 Update Instruction Register (pstate = D)

During this state, instruction shifted into the Instruction Register (IR) is latched from the Shift

instruction. On a rising edge of TCK, the controller advances to the Select_IR state if TMS is

held high or the Run-Test-Idle state If TMS is held low.

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