DSP56857 datasheet(461/662 Pages) FREESCALE

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Servicing the Host Interface

Host Interface Eight (HI8), Rev. 4

Freescale Semiconductor

16-35

HDS/HWR, and HCS) but the receive byte registers (RXH and RXL) may not be accessed

until the DMA mode is disabled.

5. Terminate the DMA controller channel to disable DMA transfers.

6. Terminate the DSC HI8 DMA mode by clearing the HM1 and HM0 bits and clearing

RREQ in the Interface Control Register (ICR).

16.10.10 Host Port Use Considerations

Careful synchronization is required when reading multi-bit registers written by another

asynchronous system. This is a common problem when two asynchronous systems are connected.

The situation exists in the Host port. However, if the port is used in the way it was designed,

proper operation is guaranteed. The considerations for proper operation are discussed below.

16.10.10.1 Host Programmer Considerations

1. Unsynchronized Reading of receive byte registers.

When reading receive byte registers, RXH or RXL, the Host programmer should use

interrupts or poll the RXDF flag indicating data is available. This guarantees the data in

the receive byte registers are stable.

2. Overwriting transmit byte registers.

The Host programmer should not write to the transmit byte registers, TXH or TXL, unless

the TXDE bit is set, indicating the transmit byte registers are empty. After writing, time

must be allowed for TXDE to update. From the rising edge of the clock effecting write of

the TX register pair high order byte (address 0x7) to the valid indication of TXDE is a

period of two DSC clock cycles. This guarantees the DSC will read stable data when it

reads the HRX register.

3. Synchronization of Status Bits from DSC-to-Host.

HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared

from inside the DSC and read by the Host Processor. The Host can not read these status

bits very quickly without regard to the clock rate used by the DSC there is a chance the

state of the bit could be changing during the read operation. This is generally not a system

problem because the bit is read correctly in the next pass of any Host polling routine.

However, if the Host holds the HCS input pin for the minimum assert time plus 1.5 Clock

cycles, the status data is guaranteed to be stable. The 1.5 Clock cycles is first used to

synchronize the HCS signal and then to block internal updates of the status bits. There is

no other minimum HCS assert time relationship to the DSC clocks. There is a minimum

HCS deassert time of 1.5 Clock cycles so that the blocking latch can be deasserted to

allow updates if the Host is in a tight polling loop. This only applies to reading status bits.

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