DSP56857 datasheet(460/662 Pages) FREESCALE

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Servicing the Host Interface

5685X Digital Signal Controller User Manual, Rev. 4

16-34

Freescale Semiconductor

2. Transfer the HTX register to the receive byte registers RXH/RXL when they are empty

(RXDF = 0). This automatically occurs. Load the Host DMA address counter from HM1

and HM0. This action sets HTDE = 1 and trigger another DSC transmit exception to write

HTX.

3. Assert the Host Request (HREQ) pin when the receive byte registers are full.

4. Enable the selected Receive Byte register on the Host data bus when HACK is asserted.

Deassert the Host Request HREQ pin.

5. If the highest register address has not been reached (i.e., RXDF = 1), post-increment the

HI8 DMA address counter to select the next register. Wait until HACK is deasserted, then

go to Step 3.

6. If the highest register address has been reached (i.e., RXDF = 0), wait until HACK is

deasserted then go to step 2. The DSC transmit exception must have written HTX (i.e.,

HTDE = 0) before Step 2 is executed.

Note:

The HOST –> DSC data transfers can occur normally in the channel not used for DMA

except when the Host must use polling and not interrupts.

Note:

The transfer of data from the HTX register to the RXH/RXL registers automatically

loads the HI8 DMA address counter from the HM1 and HM0 bits when in DMA

DSC-to-Host mode.

16.10.9.4 DSC-to-Host Processor Procedure

The following procedure outlines the typical steps the Host Processor must take to setup and

terminate a DSC-to-Host DMA transfer.

1. Setup the external DMA controller destination address, direction, byte count, and other

control registers. Enable the DMA controller channel.

2. The DSC must be configured to provide the outgoing data via polling, interrupts, or DSC

Side DMA configuration. If interrupt operation is desired HTIE must be set to enable the

HTDE interrupt. If DSC Side DMA operations are desired, set TDMAE to enable DSC

transfers when HTDE is set. This could be done with a separate Host Command exception

routine in the DSC.

3. Set HTDE and clear RXDF. This can be done with the appropriate INIT function. The

DSC Host transmit exception is activated immediately by DSC hardware which begins the

DMA transfer.

4. Perform other tasks until interrupted by the DMA controller DMA complete interrupt. The

DSC Interface Control Register (ICR), the Interrupt Status Register (ISR), and TXH/TXL

may be accessed at any time by the Host Processor (using HA0-HA2, HRW/HRD,

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