DSP56857 datasheet(453/662 Pages) FREESCALE

453 / 662 page

Servicing the Host Interface

Host Interface Eight (HI8), Rev. 4

Freescale Semiconductor

16-27

contents of this register are initialized to a pre-defined value by a hardware or software reset,

corresponding to the uninitialized interrupt vector in the MC68000 family.

Figure 16-13. Interrupt Vector Register (IVR)

See Programmer’s Sheet on Appendix page B - 144

16.10.3 Receive Byte Registers (RXH, RXL)

The Receive Byte Registers are viewed as two 8-bit read-only registers by the Host Processor.

These registers are called Receive Data High (RXH) and Receive Data Low (RXL). These two

registers receive data from the High Byte and Low Byte, respectively from the HTX register.

They are selected by three external Host Address (HA2, HA1, and HA0) inputs during a Host

Processor read operation or by an on-chip address counter in DMA operations. The Receive Byte

Registers contain valid data when the Receive Data Register Full (RXDF) bit is set. The Host

Processor may program the RREQ bit to assert the external HREQ pin when the RXDF bit is set.

This informs the Host Processor or Host DMA controller of the Receive Byte Registers full

condition. Reading the Data Register at Host Address $7 clears the RXDF bit.

•

When the HLEND bit in the Interface Control Register (ICR) is cleared, the Receive Data

•

When the HLEND bit in the ICR is set, the RXH register is located at address $7 and the

RXL register, at $6.

Figure 16-14. HI8 Receive Byte High Register (RXH)

See Programmer’s Sheet on Appendix page B - 145

* Depends on HLEND setting

Base + $3

Read

IV7

IV6

IV5

IV4

IV3

IV2

IV1

IV0

Write

Reset

00001111

Base + $6/$7*

Read

RXH

Write

Reset

00000000

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