DSP56857 datasheet(451/662 Pages) FREESCALE

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Servicing the Host Interface

Host Interface Eight (HI8), Rev. 4

Freescale Semiconductor

16-25

16.10.1.1 Host Request (HREQ)—Bit 7

This bit indicates the status of the external Host Request (HREQ) output pin if the HRMS bit is

cleared; or the external Host Transmit Receive Request (HTRQ) output pins, and HRRQ

respectively, if HRMS is set. When the HREQ status bit is cleared, it indicates the Host Request

pin, HREQ or HTRR, HTRQ and HRRQ, are deasserted and either Host Processor interrupts or

host DMA transfers are being requested.

If the HREQ status bit is set, it means the Host Request (HREQ) pin, the Host Transmit Request

(HTRQ), or Host Receive Request (HRRQ) are asserted, indicating the DSC is interrupting the

Host Processor or a Host DMA transfer request is being made. The HREQ interrupt request may

originate from one or more of two sources:

1. The receive byte registers are full

2. The transmit byte registers are empty

These conditions are indicated by the Interrupt Status Register (ISR) RXDF and TXDE status

bits, respectively. If the interrupt source has been enabled by the associated request enable bit in

the Interface Control Register (ICR); HREQ, HTRQ, or HRRQ bits is set if one or more of the

two enabled interrupt sources is set. DSC reset clears HREQ.

16.10.1.2 Host DMA Status (DMA)–Bit 6

The DMA status bit (DMA) indicates the Host Processor has enabled the DMA mode of the HI8

(HM1 or HM0 =1). When the DMA status bit is clear, it indicates the DMA mode is disabled by

the Host mode bits (HM0 and HM1) in the Interface Control Register (ICR) and no DMA

operations are pending. When DMA is set, it indicates the DMA mode is enabled and the Host

Processor should not use the active DMA channel (RXH:RXL or TXH:TXL depending on DMA

direction) to avoid conflicts with the DMA data transfers.

Note:

This bit is always 0 if HRMS = 1 in the Host Control Register because the HREQ and

HACK function is disabled, thereby disabling the Host DMA operations.

16.10.1.3 Reserved Bit–Bit 5

This bit is reserved or not implemented. It is read as, and written with 0s.

16.10.1.4 Host Flag 3 (HF3)–Bit 4

The Host Flag 3 (HF3) bit in the Interrupt Status Register indicates the state of Host Flag 3 in the

Host Control Register on the DSC Side. The HF3 bit can only be changed by the DSC Side.

Please see Figure 16-4.

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