ISL6752DBEVAL1Z datasheet(10/18 Pages) RENESAS

10 / 18 page

ISL6752

FN9181 Rev 4.00

Page 10 of 18

August 1, 2016

be set lower than 2V to ensure that the lower FETs, at

maximum duty cycle, are OFF prior to the switching of the

upper FETs.

OUTLL and OUTLR - These outputs control the lower bridge FETs,

are pulse width modulated, and operate in alternate sequence.

OUTLL controls the lower left FET and OUTLR controls the lower

right FET. The left and right designation may be switched as long

as they are switched in conjunction with the upper FET outputs,

OUTUL and OUTUR.

OUTLLN and OUTLRN - These outputs are the complements of

the PWM (lower) bridge FETs. OUTLLN is the complement of

OUTLL and OUTLRN is the complement of OUTLR. These

outputs are suitable for control of synchronous rectifiers. The

phase relationship between each output and its complement

is controlled by the voltage applied to VADJ.

VADJ - A 0V to 5.0V control voltage applied to this input sets

the relative delay or advance between OUTLL/OUTLR and

OUTLLN/OUTLRN. The phase relationship between

OUTUL/OUTUR and OUTLL/OUTLR is maintained regardless of

the phase adjustment between OUTLL/OUTLR and

OUTLLN/OUTLRN.

Voltages below 2.425V result in OUTLLN/OUTLRN being

advanced relative to OUTLL/OUTLR. Voltages above 2.575V

result in OUTLLN/OUTLRN being delayed relative to

OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero phase

difference. A weak internal 50% divider from VREF results in

no phase delay if this input is left floating.

The range of phase delay/advance is either zero or 40ns to

300ns with the phase differential increasing as the voltage

deviation from 2.5V increases. The relationship between the

control voltage and phase differential is non-linear. The gain

(

t/V) is low for control voltages near 2.5V and rapidly

increases as the voltage approaches the extremes of the

control range. This behavior provides the user increased

accuracy when selecting a shorter delay/advance duration.

When the PWM outputs are delayed relative to the SR outputs

(VADJ < 2.425V), the delay time should not exceed 90% of the

dead time as determined by RTD and CT.

VERR - The control voltage input to the inverting input of the

PWM comparator. The output of an external Error Amplifier

(EA) is applied to this input, either directly or through an

opto-coupler, for closed loop regulation. VERR has a nominal

1mA pull-up current source.

CTBUF - CTBUF is the buffered output of the sawtooth oscillator

waveform present on CT and is capable of sourcing 2mA. It is

offset from ground by 0.40V and has a nominal valley-to-peak

gain of 2. It may be used for slope compensation.

Functional Description

Features

The ISL6752 PWM is an excellent choice for low cost ZVS

full-bridge applications requiring adjustable synchronous

rectifier drive. With its many protection and control features, a

highly flexible design with minimal external components is

possible. Among its many features are a very accurate

overcurrent limit threshold, thermal protection, a buffered

sawtooth oscillator output suitable for slope compensation,

synchronous rectifier outputs with variable delay/advance

timing, and adjustable frequency.

If synchronous rectification is not required, please consider the

ISL6753 controller.

Oscillator

The ISL6752 has an oscillator with a programmable frequency

range to 2MHz, which can be programmed with a resistor and

capacitor.

The switching period is the sum of the timing capacitor charge

and discharge durations. The charge duration is determined by

CT and a fixed 200µA internal current source. The discharge

duration is determined by RTD and CT.

Where tC and tD are the charge and discharge times,

respectively, CT is the timing capacitor in Farads, RTD is the

discharge programming resistance in ohms, tSW is the

oscillator period, and fSW is the oscillator frequency. One

output switching cycle requires two oscillator cycles. The

actual times will be slightly longer than calculated due to

internal propagation delays of approximately 10ns/transition.

This delay adds directly to the switching duration, but also

causes overshoot of the timing capacitor peak and valley

voltage thresholds, effectively increasing the peak-to-peak

voltage on the timing capacitor. Additionally, if very small

discharge currents are used, there will be increased error due

to the input impedance at the CT pin. The maximum

recommended current through RTD is 1mA, which produces a

CT discharge current of 20mA.

The maximum duty cycle, D, and percent dead time, DT, can be

calculated from Equations 4 and 5:

tC 11.5 10



3 CT





(EQ. 1)

tD 0.06 RTD CT



 50 10

–





(EQ. 2)

tSW

tC tD

fSW

----------

(EQ. 3)

tSW

----------

(EQ. 4)

1 D

–

(EQ. 5)

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