ISL6752DBEVAL1Z datasheet(9/18 Pages) RENESAS

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ISL6752

FN9181 Rev 4.00

Page 9 of 18

August 1, 2016

Pin Descriptions

VDD - VDD is the power connection for the IC. To optimize noise

immunity, bypass VDD to GND with a ceramic capacitor as

close to the VDD and GND pins as possible.

VDD is monitored for supply voltage Undervoltage Lock-Out

(UVLO). The start and stop thresholds track each other

resulting in relatively constant hysteresis.

GND - Signal and power ground connections for this device.

Due to high peak currents and high frequency operation, a low

impedance layout is necessary. Ground planes and short

traces are highly recommended.

VREF - The 5.0V reference voltage output having 3% tolerance

over line, load and operating temperature. Bypass to GND with

a 0.1µF to 2.2µF low ESR capacitor.

CT - The oscillator timing capacitor is connected between this

pin and GND. It is charged through an internal 200µA current

source and discharged with a user adjustable current source

controlled by RTD.

RTD - This is the oscillator timing capacitor discharge current

control pin. The current flowing in a resistor connected

between this pin and GND determines the magnitude of the

current that discharges CT. The CT discharge current is

nominally 20x the resistor current. The PWM dead time is

determined by the timing capacitor discharge duration. The

voltage at RTD is nominally 2V.

CS - This is the input to the overcurrent comparator. The

overcurrent comparator threshold is set at 1V nominal. The CS

pin is shorted to GND at the termination of either PWM output.

Depending on the current sensing source impedance, a series

input resistor may be required due to the delay between the

internal clock and the external power switch. This delay may

result in CS being discharged prior to the power switching

device being turned off.

OUTUL and OUTUR - These outputs control the upper bridge

FETs and operate at a fixed 50% duty cycle in alternate

sequence. OUTUL controls the upper left FET and OUTUR

controls the upper right FET. The left and right designation may

be switched as long as they are switched in conjunction with

the lower FET outputs, OUTLL and OUTLR.

RESDEL - Sets the resonant delay period between the toggle of

the upper FETs and the turn on of either of the lower FETs. The

voltage applied to RESDEL determines when the upper FETs

switch relative to a lower FET turning on. Varying the control

voltage from 0V to 2V increases the resonant delay duration

from 0 to 100% of the dead time. The control voltage divided

by 2 represents the percent of the dead time equal to the

resonant delay. In practice the maximum resonant delay must

Typical Performance Curves

FIGURE 4. REFERENCE VOLTAGE vs TEMPERATURE

FIGURE 5. CT DISCHARGE CURRENT GAIN vs RTD CURRENT

FIGURE 6. DEAD TIME (DT) vs CAPACITANCE

FIGURE 7. CAPACITANCE vs FREQUENCY

-40 -25

-10

95 110

0.98

0.99

1.00

1.01

1.02

TEMPERATURE (°C)

200

400

600

800

1000

RTD CURRENT (µA)

2030

5060708090

100

RTD (kΩ)

1-104

1-103

CT = 1000pF

CT = 680pF

CT = 470pF

CT = 330pF

CT = 220pF

CT = 100pF

0.1

100

(nF)

1-103

RTD = 10kΩ

RTD = 50kΩ

RTD = 100kΩ

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