HT85F2240 datasheet(18/147 Pages) HOLTEK

18 / 147 page

Rev. 1.10

18 of 147

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A/D Flash 8051 Core Low Pin Count MCU

HT85F2230/HT85F2240

Pin Name

Function

OPT

I/T

O/T

Description

P�.1/CC1/AIN�

P�.1

P�M0

P�M1

CMOS Genera� p�rpose I/O. Register se�ected I/O mode.

CC1

PRM

CMOS Compare/Capt�re inp�t/o�tp�t for PCA mod��e 1

AIN�

ADCR�

—

ADC Inp�t Channe� �

P�.�/INT0

P�.�

P�M0

P�M1

CMOS Genera� p�rpose I/O. Register se�ected I/O mode.

INT0

IEN0

TCON

—

Externa� Interr�pt 0 Inp�t

P�.�/INT1/VREF

P�.�

P�M0

P�M1

CMOS Genera� p�rpose I/O. Register se�ected I/O mode.

INT1

IEN0

TCON

—

Externa� Interr�pt 1 Inp�t

VREF

ADCR1

—

Reference Vo�tage for ADC

P�.4/T0/AIN1

P�.4

P�M0

P�M1

CMOS Genera� p�rpose I/O. Register se�ected I/O mode.

—

Timer 0 Externa� Inp�t

AIN1

ADCR�

—

ADC Inp�t Channe� 1

P�.�/T1/AIN�

P�.�

P�M0

P�M1

CMOS Genera� p�rpose I/O. Register se�ected I/O mode.

—

Timer 1 Externa� Inp�t

AIN�

ADCR�

—

ADC Inp�t Channe� �

P�.6/T�/AIN�

P�.6

P�M0

P�M1

CMOS Genera� p�rpose I/O. Register se�ected I/O mode.

T�

—

Timer � Externa� Inp�t

AIN�

ADCR�

—

ADC Inp�t Channe� �

P�.7/T�EX/AIN4

P�.7

P�M0

P�M1

CMOS Genera� p�rpose I/O. Register se�ected I/O mode.

T�EX

—

Timer � capt�re trigger

AIN4

ADCR�

—

ADC Inp�t Channe� 4

RESET/ICPCK/

TCK

RESET

—

Reset pin

ICPCK

—

ICP C�ock Inp�t

TCK

—

Deb�g C�ock Inp�t� on�� for EV chip

VDD

—

PWR

—

Positive Power s�pp�� for CORE

VSS

—

PWR

—

Negative Power s�pp��

Note: I/T: Inp�t t�pe;

O/T: O�tp�t t�pe

OPT: Optiona� b� register option

PWR: Power;

ST: Schmitt Trigger inp�t

CMOS: CMOS o�tp�t;

AN: Ana�og inp�t pin

HXT: high freq�enc� cr�sta� osci��ator

Where devices exist in more than one package type the table reflects the situation for the package with the

largest number of pins. For this reason not all pins described in the table may exist on all package types.

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