HT85F2240 datasheet(85/147 Pages) HOLTEK

85 / 147 page

Rev. 1.10

8� of 147

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A/D Flash 8051 Core Low Pin Count MCU

HT85F2230/HT85F2240

Interrupt Operation

A Timer Counter overflow, an active edge or level on the external interrupt pin, a comparator

output changes state or A/D conversion completion etc, will all generate an interrupt request by

setting their corresponding request flag. When this happens, if the interrupt enable bit is set, then

the Program Counter, which stores the address of the next instruction to be executed, will be

transferred onto the stack. The Program Counter will then be loaded with a new address which

will be the value of the corresponding interrupt vector. The microcontroller will begin then fetch

its next instruction from this interrupt vector. The instruction at this vector will jump to another

section of program which is known as the interrupt service routine. Here is located the code to

control the appropriate interrupt. The interrupt service routine must be terminated with a RETI

instruction, which retrieves the original Program Counter address from the stack and allows the

microcontroller to continue with normal execution at the point where the interrupt occurred.

The EAL is used to control the whole interrupt function enable or disable and it has to be cleared

using the application program.

The various interrupt enable bits, together with their associated request flags, are shown in the

following diagram with their order of priority. Interrupts with higher priority can stop lower

priority ones. All interrupts are categorised into four priority levels.

0�H

0BH

�BH

7�H

7BH

Legend

xxx Req�est F�ag – a�to reset in ISR

Exx Enab�e Bit

EAL

IE0

INT0 Pin

EX0

TF0

Timer 0

ET0

TF�/EXF�

Timer �

ET�/EXEN�

IADC

ADC

EADC

TBF

Time Base

ETB

EAL

IE1

INT1 Pin

EX1

TF1

Timer 1

ET1

1�H

1BH

Low

Priorit�

High

Vector

Req�est

F�ags

Enab�e

Bits

Master

Enab�e

Interr�pt

Name

4�H

4BH

EAL

CCU0F

CCU0

ECCU0

CCU1F

CCU1

ECCU1

LVDF

LVD

ELVD

EAL

8BH

xxx Req�est F�ag – no a�to reset in ISR

Interrupt Structure

Note that if one interrupt requests occur during the other interrupt interval, although the interrupt

will not be immediately serviced, the request flag will still be recorded and the next interrupt

request will take place according to the interrupt priority. If the stack is full, the interrupt request

will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack must be prevented from becoming full.

When an interrupt request is generated, it takes several instruction cycles before the program jumps

to the interrupt vector.

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