HT85F2240 datasheet(73/147 Pages) HOLTEK

73 / 147 page

Rev. 1.10

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A/D Flash 8051 Core Low Pin Count MCU

HT85F2230/HT85F2240

SRST Register Software Reset

A software reset will be generated after two consecutive instructions to write a high value to the

SRSTREQ bit in the SRST register. The same bit can be used to identify the reset source.

SRST Register

SFR Address: F7h

Bit

Labe�

—

SRSTREQ

R/W

—

R/W

POR

—

Bit 7~1

Unimplemented, read as “0”

Bit 0

SRSTREQ: Software reset request.

Writing a ‘0’ value to this bit will have no effect.

A single ‘1’ value write to this bit will have no effect.

Two consecutive ‘1’ value writes to this bit will generate a software reset.

Reading this bit can indicate the last reset source:

0: No software reset

1: Software reset

This bit must be cleared by the application program as it will not be automatically

cleared by hardware.

WDTCR Register Software Reset

A WDTCR software reset will be generated when a value other than “10101” or “01010”, exist in

the highest five bits of the WDTCR register. The WRF bit in the RSTSRC register will be set high

when this occurs, thus indicating the generation of a WDTCR software reset.

WDTCR Register

SFR Address: 96h

Bit

Name

WE4

WE�

WE1

WE0

—

WDTCS

R/W

—

R/W

POR

—

Bit 7~ 3

WE4 ~ WE0: WDT function software control

10101: Disable

01010: Enable - default

Other values: Reset MCU

If the MCU reset is caused by WE[4:0] in WDTC software reset, the WRF flag of

RSTSRC register will be set.

Bit 2~1

Unimplemented, read as “0”

Bit 0

WDTCS: Watchdog clock (fWDT) selection

Described elsewhere

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