DS31256 datasheet(101/183 Pages) MAXIM

101 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

101 of 183

RDQFFT

Receive Done-Queue FIFO Flush Timer

0744h

Bit #

Name

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

Default

Bit #

Name

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

Default

Note: Bits that are underlined are read-only, all other bits are read-write.

Bits 0 to 15/Receive Done-Queue FIFO Flush Timer Control Bits (TC0 to TC15). Please note that on system

reset, the timer is set to 0000h, which is defined as an illegal setting. If the receive done-queue FIFO is to be

activated (RDQFE = 1), then the host must first configure the timer to a proper state and then set the RDQFE bit to

one.

0000h = illegal setting

0001h = timer count resets to 1

FFFFh = timer count resets to 65,536

RDMAQ

Receive DMA Queues Control

0780h

Bit #

Name

n/a

RDQF

RDQFE

RFQSF

RFQLF

n/a

RFQFE

Default

Bit #

Name

n/a

RDQT2

RDQT1

RDQT0

Default

Note: Bits that are underlined are read-only, all other bits are read-write.

Bit 0/Receive Free-Queue FIFO Enable (RFQFE). See Section 9.2.3 for details.

Bit 2/Receive Free-Queue Large Buffer FIFO Flush (RFQLF). See Section 9.2.3 for details.

Bit 3/Receive Free-Queue Small Buffer FIFO Flush (RFQSF). See Section 9.2.3 for details.

Bit 4/Receive Done-Queue FIFO Enable (RDQFE). To enable the DMA to burst write descriptors to the done

queue, this bit must be set to 1. If this bit is set to 0, messages are written one at a time.

0 = done-queue burst-write disabled

1 = done-queue burst-write enabled

Bit 5/Receive Done-Queue FIFO Flush (RDQF). When this bit is set to 1, the internal done-queue FIFO is

flushed by sending all data into the done queue. This bit must be set to 0 for proper operation.

0 = FIFO in normal operation

1 = FIFO is flushed

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