TMS320DM6431 datasheet(107/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

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SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

The Sub-Block 1 Minor Configuration Options are independent from the Sub-Block 0 Minor Configuration

Options. The user can independently select the appropriate Minor Configuration Option for each

Sub-Block.

As shown in Table 3-42 through Table 3-44, the configuration choices of the EMIFA/VPSS Sub-Block 1

are determined by the following PINMUX register fields:

• PINMUX0 register fields AEM, CS3SEL, CS4SEL, and CS5SEL.

The following is an example on how to read Table 3-42 through Table 3-44 using Sub-Block 1 Minor

Configuration E1 as an example:

• The PINMUX Selection Fields columns indicate that Sub-Block 1 Minor Configuration Option E1 is

selected through setting PINMUX0 fields to AEM = 5, CS3SEL = 0/1 (based on the desired pin choice),

CS4SEL = 0/1 (based on the desired pin choice), and CS5SEL = 0/1 (based on the desired pin

choice).

• The Resulting Peripherals/Pins columns show the functional pins resulting from the PINMUX setting.

For example, you automatically get EMIFA pins EM_D[7:0], EM_A[2:1], and EM_CS2 in addition to at

least 15 GPIO pins in Minor Config Option E1 (GP[31:22], GP[11:10], and GP[7:5]). If you program

CS3SEL = 1, CS4SEL = 0, and CS5SEL = 0, you also get EM_CS3, GP[32], and GP[33].

3.7.3.11.5 EMIFA/VPSS Sub-Block 2 Configuration Choices

The 3 pins in the EMIFA/VPSS Sub-Block 2 are standalone (non-multiplexed) pins. They always function

as EMIFA control pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE. No pin mux selection is necessary

for this Sub-Block.

3.7.3.11.6 EMIFA/VPSS Sub-Block 3 Configuration Choices

The 8 pins in the EMIFA/VPSS Sub-Block 3 are multiplexed between:

• EMIFA Address Pins EM_A[12:5]

• GPIO pins GP[96:89]

The pin functions in the EMIFA/VPSS Sub-Block 3 are determined by the following PINMUX register

fields:

• PINMUX0.AEM

Once the Major Configuration Option for the EMIFA/VPSS Block (see Section 3.7.3.11.2, EMIFA/VPSS

Block Major Configuration Choices) is chosen, no further actions are necessary to refine the EMIFA/VPSS

Sub-Block 3 pin selection. For instructions on configuring the EMIFA/VPSS Block, see Section 3.7.3.11.1,

EMIFA/VPSS Block Pin Selection Procedure.

Table 3-45 summarizes the pin selections in the EMIFA/VPSS Sub-Block 3 based on the PINMUX

selections.

Table 3-45. EMIFA/VPSS Sub-Block 3 Configuration Choices

MAJOR

PINMUX SELECTION FIELD

RESULTING PERIPHERALS/PINS

CONFIG

AEM

EMIFA

GPIO

OPTION

000

GP[96:89]

001

EM_A[12:5]

101

GP[96:89]

The following is an example on how to read Table 3-45 using Sub-Block 3 Major Configuration B as an

example:

• The PINMUX Selection Fields columns indicate that Sub-Block 3 Major Configuration Option B is

selected through setting PINMUX0.AEM = 001b.

• The Resulting Peripherals/Pins columns show the functional pins resulting from the PINMUX setting. In

Major Configuration B, the user gets EMIFA address pins EM_A[12:5] from Sub-Block 3.

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