TMS320DM6431 datasheet(106/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

3.7.3.11.4 EMIFA/VPSS Sub-Block 1 Configuration Choices

Table 3-42 through Table 3-44 show the configuration choices in the EMIFA/VPSS Sub-Block 1. For

instructions on how to use the different configuration choices tables for the EMIFA/VPSS Block and

Sub-Blocks, see Section 3.7.3.11.1, EMIFA/VPSS Block Pin Selection Procedure.

Before using Table 3-42 through Table 3-44 to configure the details of the EMIFA/VPSS Sub-Block 1, the

user should first select the Major Configuration Option for the EMIFA/VPSS Block (see Section 3.7.3.11.2,

EMIFA/VPSS Block Major Configuration Choices). After determining the Major Configuration Option (A, B,

or E), the user can now use Table 3-42 through Table 3-44 to refine the Sub-Block 1 pin selections.

1. Go to the table with the Major Configuration Option chosen from Table 3-38.

2. Each Major Configuration Option is further divided down into multiple Minor Configuration Options.

Select a Minor Configuration Option that best suits the application need.

3. Within the chosen Minor Configuration Option, further refine the detailed pin configurations by selecting

the settings of PINMUX0 fields CS3SEL, CS4SEL, and CS5SEL.

4. The PINMUX Selection Fields columns give the user the settings needed to program the PINMUX0

Table 3-42. EMIFA/VPSS Sub-Block 1 Configuration Choice A(1)

MAJOR

MINOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG

AEM

OTHERS

EMIFA

GPIO

OPTION

Cfg Summary

No EMIFA

29 GP pins

CS3SEL = 0

000

CS4SEL = 0

0 = GP[33:5]

CS5SEL = 0

(1)

Italics indicate mandatory settings for a given Minor Configuration option.

Table 3-43. EMIFA/VPSS Sub-Block 1 Configuration Choice B(1)

MAJOR

MINOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG

AEM

OTHERS

EMIFA

GPIO

OPTION

8-bit EMIFA (Async)

Cfg Summary

10-to-13 GP pins

Pinout Mode 1

EM_D[7:0], EM_CS2,

Basic Pins You Get

0 = GP[31:22]

EM_A[4:0], EM_BA[1:0]

001

CS3SEL = 0,1

1 = EM_CS3

0 = GP[13]

CS4SEL = 0,1

1 = EM_CS4

0 = GP[32]

CS5SEL = 0,1

1 = EM_CS5

0 = GP[33]

(1)

Italics indicate mandatory setting for a given Minor Configuration option.

Table 3-44. EMIFA/VPSS Sub-Block 1 Configuration Choice E(1)

MAJOR

MINOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG

AEM

OTHERS

EMIFA

GPIO

OPTION

8-bit EMIFA (NAND)

Cfg Summary

15-to-18 GP pins

Pinout Mode 5

Basic Pins You Get

EM_D[7:0], EM_A[2:1], EM_CS2

0 = GP[31:22, 11:10, 7:5]

101

CS3SEL = 0,1

1 = EM_CS3

0 = GP[13]

CS4SEL = 0,1

1 = EM_CS4

0 = GP[32]

CS5SEL = 0,1

1 = EM_CS5

0 = GP[33]

(1)

Italics indicate mandatory setting for a given Minor Configuration option.

Device Configurations

106

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