PC87334VLJ datasheet(18/102 Pages) NSC

18 / 102 page

20 Configuration Registers

21 OVERVIEW

Ten registers constitute the Base Configuration Register

set and control the PC87334VLJPC87334VJG set-up In

general these registers control the enabling of major func-

tions (FDC UARTs parallel port pin functionality etc) the

IO addresses of these functions and whether they power-

down via hardware control or not These registers are the

Function Enable Register (FER) Function Address Register

(FAR) Power and Test Register (PTR) Function Control

er Management Control Register (PMC) the Tape UARTs

and Parallel Port Configuration Register (TUP) and the Su-

perIO (SIO) Identification Register (SID) the Advanced

SIO Configuration Register (ASC) and the Infrared Configu-

ration Register (IRC)

During reset the PC87334VLJPC87334VJG loads a set of

default values selected by a hardware strapping option into

the first three Configuration Registers The FCR PCR PMC

TUP SID ASC and IRC registers can only be accessed by

software

An index and data register pair are used to read and write

the configuration registers Each Configuration Register is

pointed to the value loaded into the Index Register The

data to be written into the Configuration Register is trans-

ferred via the Data register A Configuration Register is read

in a similar way (ie by pointing to it via the Index Register

and then reading its contents via the Data Register)

Accessing the Configuration Registers in this way requires

only two system IO addresses Since IO address space is

shared by other devices the Index and Data Registers can

still be inadvertently accessed To reduce the chances of an

inadvertent access a simple procedure has been devel-

oped It is described in Section 22

22 SOFTWARE CONFlGURATlON

If the system requires access to the Configuration Registers

after reset the following procedure must be used to change

data in the registers

1 Determine the default location of the PC87334VLJ

PC87334VJG Index Register

Check the four possible locations (see Table 2-1) by

reading them twice The first byte is the ID byte 88h al-

though read-after-write always brings the value of the

written byte The second byte read is always 00h Com-

pare the data read with the ID byte and then 00h A

match occurs at the correct location Note that the ID

byte is only issued from the Index Register during the first

read after a reset Subsequent reads return the value

loaded into the Index Register Bits 4-6 are reserved and

always read 0

2 Load the Configuration Registers

A Disable CPU interrupts

B Write the index of the Configuration Register (00h –

0Eh) to the Index Register one time

C Write the correct data for the Configuration Register in

two consecutive write accesses to the Data Register

D Enable CPU interrupts

3 Load the Configuration Registers (read-modify-write)

A Disable CPU interrupts

B Write the index of the Configuration Register (00h –

0Eh) to the Index Register one time

C Read the configuration data in that register via the

Data Register

D Modify the configuration data

E Write the changed data for the Configuration Register

in two consecutive writes to the Data Register The

F Enable CPU interrupts

A single read access to the Index and Data Registers can

be done at any time without disabling CPU interrupts When

the Index Register is read the last value loaded into the

Index Register is returned When the Data Register is read

the Configuration Register data pointed to by the Index Reg-

ister is returned

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