PC87334VLJ datasheet(34/102 Pages) NSC

34 / 102 page

30 FDC Register Description (Continued)

TABLE 3-7 Default Precompensation Delays

Data Rate

Precompensation Delay

(24 MHz and 48 MHz)

2 Mbps

208 ns

1 Mbps

417 ns

500 kbps

1250 ns

300 kbps

1250 ns

250 kbps

1250 ns

D1 – 0

Data Rate Select 10

These bits determine the

data rate for the floppy controller See Table 3-8 for

the corresponding data rate for each D10 value

pair The data rate select bits are unaffected by a

software reset and are set to 250 kbps after a hard-

ware reset

TABLE 3-8 Data Rate Select Encoding

Bit 1

TUP

Data Rate Select

MFM

1 Mbps

500 kbps

300 kbps

250 kbps

2 Mbps

Illegal

This feature is not tested

317 Data Register (FIFO)

ReadWrite

The FIFO (readwrite) is used to transfer all commands

data and status between the mP and the FDC During the

Command Phase the mP writes the command bytes into the

FIFO after polling the RQM and DIO bits in the MSR During

the Result Phase the mP reads the result bytes from the

FIFO after polling the RQM and DIO bits in the MSR

Enabling the FIFO and setting the FIFO threshold is done

via the Configure command If the FIFO is enabled only the

Execution Phase byte transfers use the 16-byte FIFO The

FIFO is always disabled during the Command and Result

Phases of a controller operation A software reset will not

disable enabled FIFO if the Lock bit is set in the Lock Com-

mand After a hardware reset the FIFO is disabled to main-

tain compatibility with PC-AT systems

The 16-byte FIFO can be used for DMA Interrupt or soft-

ware polling type transfers during the execution of a read

write format or scan command In addition the FIFO can

be put into a Burst or Non-Burst mode with the Mode com-

mand In the Burst mode DRQ or IRQ6 remains active until

all of the bytes have been transferred to or from the FIFO In

the Non-Burst mode DRQ or IRQ6 is deasserted for 350 ns

to allow higher priority transfer requests to be serviced The

Mode command can also disable the FIFO for either reads

or writes separately The FIFO allows the system a larger

latency without causing a disk overrununderrun error The

FIFO is typically utilized with multitasking operating systems

andor when running systems at or above a 1 Mbps data

rate In its default state the FIFO is disabled and contains a

zero threshold The default state is entered after a hardware

reset

Data Register (FIFO)

DESC

Data 70

RESET

Byte Mode

COND

During the Execution Phase of a command involving a data

transfer tofrom the FIFO

the system must respond

to a data transfer service request based on the following

formula

Maximum Allowable Data Transfer Service Time

(THRESH a 1) c 8 c tDRP b (16 c tICP)

This formula is good for all data rates with the FIFO enabled

or disabled THRESH is a four bit value programmed in the

Configure command which sets the FIFO threshold If the

FIFO is disabled THRESH is zero in the above formula The

last term of the formula (16 c tICP) is an inherent delay due

to the microcode overhead required by the FDC This delay

is also data rate dependent See Table 9-1 for the tDRP and

tICP times See Section 1032 for a description of tDRP and

tICP

The programmable FIFO threshold (THRESH) is useful in

adjusting the floppy controller to the speed of the system In

other words a slow system with a sluggish DMA transfer

capability uses a high value of THRESH giving the system

more time to respond to a data transfer service request

(DRQ for DMA mode or IRQ6 for Interrupt mode) Converse-

ly a fast system with quick response to a data transfer serv-

ice request uses a low value of THRESH

318 Digital Input Register (DIR)

Read Only

This diagnostic register is used to detect the state of the

DSKCHG disk interface input and some diagnostic signals

The function of this register depends on its mode of opera-

tion When in the PC-AT mode the D6 – 0 are TRI-STATE to

avoid conflict with the fixed disk status register at the same

address DIR is unaffected by a software reset

DIRPC-AT Mode

DESC

DSKCHG

XXXXXXX

RESET

COND

Disk Changed

Active high status of DSKCHG disk

interface input During power-down this bit is invalid

if it is read by the software

D6 – 0

Unused

by the FDC (at TRI-STATE) The bits are

used by the Hard Disk Controller Status Register

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