PC87334VLJ datasheet(26/102 Pages) NSC

26 / 102 page

20 Configuration Registers (Continued)

Bit 4

PD and IDLE (FDC power management output pins)

enable bit

When this bit is 0 pins 4341 (PQFPTQFP) and

4543 (PQFPTQFP) are MTR1 and DR1 respectively

When this bit is 1 pins 4341 (PQFPTQFP) and

4543 (PQFPTQFP) are IDLE and PD respectively

Bit 5

Selective Lock bit This bit enables locking of the fol-

lowing configuration bits bit 5 of PMC bit 4 of FER

bits 0 – 7 of FAR bits 2 – 3 of PTR bits 6 – 7 of FCR

and bit 0 of TUP Unlike bit 6 of PTR it does not lock

all the configuration bits

Once this bit is set by software it can only be cleared

by a hardware reset This bit should be used instead of

bit 6 of PTR if a configuration bit should be dynamically

modified by software (like PMC bits)

When this bit is 0 bit 6 of PTR can be used to lock all

configuration registers

When this bit is 1 the above configuration bits cannot

be modified A hardware reset clears this bit

Bit 6

Parallel Port Multiplexor (PPM) TRI-STATE enable bit

This bit enables reduction in power consumption

(when the SuperIO is in power-down mode or the par-

allel port is disabled) by placing the PPM outputs in

TRI-STATE and blocking the PPM inputs

When this bit is 0 the parallel port pins are enabled

When this bit is 1 and either the parallel port is dis-

abled or the SuperIO is in power-down mode the out-

puts of the Parallel Port pins (except IRQ5 and IRQ7)

are in TRI-STATE and the inputs are blocked to re-

duce their leakage currents

The values of the blocked inputs are

BUSYe1

PEe0 SLCTe0 ACKe1 and ERRe1

Bit 7

Reserved

maintain

compatibility

with

future

SuperIO devices this bit must not be modified when

this register is written Use read-modify-write to pre-

serve the value of this bit

257 Tape UARTs and Parallel Port Configuration

The TUP Register is cleared to 0XX0000X on reset

Bit 0

CLK48 Clock divider enable bit

When a 48 MHz clock is used this bit should be 1

When a 24 MHz clock is used this bit should be 0

When this bit is 0 the clock for all the PC87334 mod-

ules is X1OSC (ie 24 MHz)

When this bit is 1 the clock of all PC87334 modules

except the FDC is X1OSC divided by 2 (ie 482 e

24 MHz) and the FDC clock depends on bit 1 of TUP

During reset the value of CLK48 pin (pin 5755

(PQFPTQFP) ) is latched into this bit

This bit should not be modified by the user

Bit 1

FDC’s 2 Mbps enable bit

When this bit is 0 a 2 Mbps data rate is not supported

by the FDC and the FDC clock is 24 MHz (X1OSC

when bit 0 of TUP is 0 or X1OSC divided by 2 when

bit 0 of TUP is 1)

When this bit is 1 2 Mbps is supported by the FDC

and the FDC clock is 48 MHz (X1OSC when bit 0 of

TUP is 1) Bit 0 of TUP must be set to 1 and a 48 MHz

clock must be used to support a 2 Mbps data rate

The operating voltage should be 5V (See Section 50

FDC Functional Description)

Bit 2

EPP Timeout Interrupt Enable bit

When this bit is 0 the EPP timeout interrupt is masked

When this bit is 1 the EPP timeout interrupt is generat-

ed on the selected IRQ line (IRQ5 or IRQ7) according

to PCR 6

Bit 3

UART 1 clock divisor control (MIDI baud rate configu-

ration) bit

When this bit is 0 the UART 1 Baud Rate Generator is

fed by the master clock divided by 13

When this bit is 1 the UART 1 Baud Rate Generator is

fed by the master clock divided by 12 This bit should

be set to 1 to support MIDI baud rates

Bit 4

UART 2 clock divisor control (MlDI baud rate configu-

ration) bit

When this bit is 0 the UART 2 Baud Rate Generator is

fed by the master clock divided by 13

When this bit is 1 the UART 2 Baud Rate Generator is

fed by the master clock divided by 12 This bit should

be set to 1 to support MIDI baud rates

Bit 5

PD status bit This bit holds the FDC power-down

state as defined for the PD pin even when pin 4543

(PQFPTQFP) is not configured as PD This bit is read

only

Bit 6

IDLE status bit This bit holds the FDC idle state as

defined for the IDLE pin even when pin 4341 (PQFP

TQFP) is not configured as IDLE and when IDLE is

masked by bit 7 of TUP This bit is read only

Bit 7

IDLE pin mask bit This bit masks the IDLE output pin

(but not the IDLE status bit) This bit is ignored when

pin 4341 (PQFPTQFP) is not configured as idle

When this bit is 0 the IDLE output pin is unmasked

The IDLE pin drives the value of the FDC idle state

When this bit is 1 the IDLE output pin is masked The

IDLE pin is driven low

258 SuperIO Identification Register

(SID Index e 08h)

The SID Register is accessed like the other configuration

registers through the Index Register This read-only register

is used to identify the PC87334 device

76543

01010XXX

Super IO Identification

Reg (SID)

Index e 08h

259 Advanced SuperIO Configuration Register

(ASC Index 09h)

During reset bits 0 – 2 and bit 5 are initialized to 0 and bits

6 – 7 are initialized to 1

Bit 0

IRQ5DRATE0 select

0 Pin 98 (PQFP) or pin 96 (TQFP) is IRQ5

1 Pin 98 (PQFP) or Pin 96 (TQFP) is ADRATE0 open

drain output

Selection of parallel port interrupt pin (IRQ5 or IRQ7)

via bits 1 and 0 of FAR and via bit 3 of PTR is ignored

and IRQ7 is used as the parallel port interrupt Unlike

IRQ5 ADRATE0 is not controlled by bits 5 and 6 of

PCR It has the same value as DRATE0

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