PC87334VLJ datasheet(24/102 Pages) NSC

24 / 102 page

20 Configuration Registers (Continued)

253 Power and Test Register (PTR Index e 02h)

This register determines the power-down method used

when the power-down pin (PWDN) is asserted (crystal and

clocks vs clocks only) and whether hardware power-down

is enabled It also provides a bit for software power-down of

all enabled functions It selects whether IRQ7 or IRQ5 is

associated with LPTB It puts the enabled UARTs into their

test mode

Independent of this register the floppy disk controller can

enter low power mode via the Mode Command or the Data

Rate Select Register

Bit 0

Setting this bit causes all enabled functions to be

powered-down

If the crystal power-down option is selected (see Bit 1)

the crystal is also powered-down All register data is

retained when the crystal or clocks are stopped The

FDC UARTs IDE and Parallel Port pins are affected

by this bit when the relevant PMC register bits are set

Note

Bits 2 and 3 of PCR can affect the function of the parallel port

power-down mode

Bit 1

When the Power-Down pin or Bit 0 is asserted this bit

determines whether the enabled functions have their

internal clocks stopped (Bit 1 e 0) or the external

crystal (Bit 1 e 1) is stopped Stopping the crystal is

the lowest power consumption state of the part How-

ever if the crystal is stopped a finite amount of time

(E8 ms) is required for crystal stabilization once the

Power-Down pin (PWDN) or Bit 0 is deasserted If all

internal clocks are stopped but the crystal continues

to oscillate no stabilization period is required after the

Power-Down pin or Bit 0 is deasserted

Bit 2

Reserved This bit must be set to 0

Bit 3

Setting this bit associates the parallel port with IRQ7

when the address for the parallel port is 378 – 37Fh

(LPTB) This bit is a ‘‘don’t care’’ when the parallel

port address is 3BC – 3BEh (LPTA) or 278 – 27Fh

(LPTC)

Bit 4

Setting this bit puts UART1 into a test mode which

causes its Baud Out clock to be present on its SOUT1

pin if the Line Control Register bit 7 is set to 1

Bit 5

Setting this bit puts UART2 into a test mode which

causes its Baud Out clock to be present on its SOUT2

pin if the Line Control Register bit 7 is set to 1

Bit 6

Setting this bit to 1 prevents all further write accesses

to the Configuration Registers Once it is set by soft-

ware it can only be cleared by a hardware reset After

the initial hardware reset it is zero

Bit 7

When not in EPP or ECP modes this bit selects Com-

patible or Extended mode operation and thus controls

whether Pulse or Level interrupts are used

Set this bit to 0 for Compatible mode Pulse interrupt

Set this bit to 1 for Extended mode Level interrupt

In EPP mode this bit selects Regular or Automatic

bidirectional mode thus determining the direction

control method

Set this bit to 0 for Automatic mode Host RD and WR

signals control the direction

Set this bit to 1 for Regular mode bit 5 of CTR con-

trols the direction

After the initial hardware reset this bit is 0

254 Function Control Register (FCR Index e 03h)

This register determines several pin options

It selects between Data Rate output and automatic media

sense inputs

It enables the Parallel Port Multiplexor (PPM) and switches

between internal and external drives

For Enhanced Parallel Port operation it enables the

IOCHRDY and ZWS options and pins

On reset bits 2 – 7 of FCR are cleared

Bit 0

Media SenseData Rate select bit When this bit is 0

the MSEN0 – 1 pins are Media Sense inputs When

this bit is 1 the DRATE0 – 1 pins are Data Rate out-

puts On reset the VLD0 pin is sampled and its value

placed into this bit When this bit is 0 bits 5 – 7 of TDR

are valid When this bit is 1 bits 2 – 7 of TDR are TRI-

STATE during read When bit 2 of ASC register is 1

TDR is not controlled by this bit

Bit 1

When bit 1 e 0

Pin 5654 (PQFPTQFP) is IDEHI DRIDD1VLD0

3F3 read decoding is not supported

Pin 5957 (PQFPTQFP) is IOCS16 DRID0 IDE

DMA is not supported

IDEACK is assumed inactive

The selection of IDEHI and IOCS16 or DRID10 is

via bit 2 of ASC

When bit 1 e 1

IDE DMA and 3F3-read decoding are supported

Pin 5654 (PQFPTQFP) is 3F3RD VLD0

Pin 5957 (PQFPTQFP) is IDEACK input

3F3-read decoding is as follows

3F3RD is asserted during IO reads from 3F3h ie

when A9 – 0 e 3F3h (A10 not decoded) and AEN e 0

and RD e 0

Note

To avoid contention on the data bus during TDR read the

3F3RD should be used only when bit 2 of ASC is 0 and bit 0

of FCR is 1

Bit 2

PrinterFloppy Parallel Port Multiplexor (PPM) enable

bit When this bit is 0 the port is configured as a paral-

lel port When this bit is 1 the port is configured as a

floppy drive port See PNF pin description for further

information The DRV2 PNF pin is read as DRV2 bit

regardless of bit 2 of FCR

Bit 3

Parallel Port Multiplexor (PPM) float control bit When

this bit is 0 the PPM pins are driven When this bit is

1 the PPM pins are in TRI-STATE mode and the pull-

ups are disconnected

Bit 3 is functional whether or not the PPM is config-

ured (when bit 2 of FCR is 0)

When bit 3 e 1 the PPM outputs are in TRI-STATE

and the inputs are blocked to reduce their leakage

current

The values of the blocked inputs are

BUSYe1 PEe0 SLCTe0 ACKe1 and ERRe1

Note

To avoid undefined FDC inputs the PPM can be disabled be-

fore this bit is set

Bit 4

Logical Drive Exchange bit This bit allows software to

exchange the physical floppy-disk control signals as-

signed to drives 0 and 1 thus exchanging the logical

drives A and B

This is accomplished by exchanging control of the

DR0 and MTR0 pins with the DR1 and MTR1 pins

The result is undefined if four drive mode is selected

(FER4 e 1) Table 2-9 shows the associations be-

tween the Configuration Register bit the Digital Out-

put Register bits (DRVSEL01 and MTR01) and the

drive and motor control pins (DR01 and MTR01)

When bit 2 of ASC register is 1 the logical drive ex-

change function is controlled by bits 2-3 of TDR

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