AS4C64M32MD2-25BCN datasheet(79/129 Pages) ALSC

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7.2 Vref Tolerances

The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in Figure 7.1.

It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VDD

stands for VDDCA for VRefCA and VDDQ for VRefDQ. VRef(DC) is the linear average of VRef(t) over a very long

period of time (e.g. 1 sec) and is specified as a fraction of the linear average of VDDQ or VDD2 also over a very long

period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table 24. Furthermore VRef(t) may

temporarily deviate from VRef(DC) by no more than +/- 1% VDD. Vref(t) cannot track noise on VDDQ or VDDCA if this

would send Vref outside these specifications

Figure 7.1 — Illustration of VRef(DC) tolerance and VRef ac-noise limits

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on

VRef. “VRef “ shall be understood as VRef(DC), as defined in Figure 7.1.

This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low

level and therefore the time to which setup and hold is measured. Devices will function correctly with appropriate

timing deratings with VREF outside these specified levels so long as VREF is maintained between 0.44 x VDDQ (or

VDDCA) and 0.56 x VDDQ (or VDDCA) and so long as the controller achieves the required single-ended AC and DC

input levels from instantaneous VREF (see the Single-Ended AC and DC Input Levels for CA and CS# Inputs Table

and Single-Ended AC and DC Input Levels for DQ and DM.) Therefore, system timing and voltage budgets need to

account for VREF deviations outside of this range.

This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage

associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of

VDD) are included in LPDDR2 timings and their associated deratings.

AS4C64M32MD2-25BCN

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