AS4C64M32MD2-25BCN datasheet(52/129 Pages) ALSC

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4.11

Mode Register Read Command

The Mode Register Read command is used to read configuration and status data from mode registers.

The Mode Register Read (MRR) command is initiated by having CS# LOW, CA0 LOW, CA1 LOW, CA2 LOW, and

CA3 HIGH at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r- CA4r}. The mode

of the clock where the Mode Register Read Command is issued. Subsequent data beats contain valid, but undefined

content, except in the case of the DQ Calibration function DQC, where subsequent data beats contain valid content as

described in “DQ Calibration”. All DQS, DQS# shall be toggled for the duration of the Mode Register Read burst.

The MRR command has a burst length of four. The Mode Register Read operation (consisting of the MRR command

and the corresponding data traffic) shall not be interrupted. The MRR command period (tMRR) is 2 clock cycles. Mode

DQS, DQS# shall be toggled

Transitioning data

Undefined

CK#

CA[9:0]

CMD

DQS#

DQS

RL = 3

tMRR = 2

DOUT

Figure 4.34 — Mode Register Read timing example: RL = 3, tMRR = 2

NOTE 1 Mode Register Read has a burst length of four.

NOTE 2 Mode Register Read operation shall not be interrupted.

NOTE 3 Mode Register data is valid only on DQ[0-7] on the first beat. Subsequent beats contain valid,

but undefined data. DQ[8-max] contain valid, but undefined data for the duration of the MRR burst.

NOTE 4 The Mode Register Command period is tMRR. No command (other than Nop) is allowed during this period.

NOTE 5 Mode Register Reads to DQ Calibration registers MR32 and MR40 are described in

the section on DQ Calibration.

NOTE 6 Minimum Mode Register Read to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock

cycles.

NOTE 7 Minimum Mode Register Read to Mode Register Write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1

clock cycles.

The MRR command shall not be issued earlier than BL/2 clock cycles after a prior Read command and WL + 1 +

BL/2 + RU( tWTR/tCK) clock cycles after a prior Write command, because read-bursts and write-bursts shall not be

truncated by MRR. Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the

effective burst length of the truncated burst should be used as “BL.”

AS4C64M32MD2-25BCN

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