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AS4C64M32MD2-25BCN bảng dữ liệu(HTML) 37 Page - Alliance Semiconductor Corporation

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4.7 Write Data Mask
One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices, consistent with the
implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data byte (DQ) for any given
cycle of the burst. Data mask has identical timings on write operations as the data bits, though used as input only, is
internally loaded identically to data bits to insure matched system timing.
Data Mask Timing
Data Mask Function, WL = 2, BL = 4 shown, second DQ masked
Figure 4.20 — LPDDR2-SX: Write data mask
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