eZ80F91 datasheet(14/30 Pages) ZILOG

14 / 30 page

PS026102-1207

Pin Description

Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP

Product Specification

TDI/ZDA

Input

JTAG Data Input pin.

GND

VSS/Ground (0 V).

TRIGOUT

Output

Active High trigger event indicator.

TCK/ZCL

PU 10 k

Ω Input

JTAG Input. High on reset enables ZDI mode;

Low on reset enables OCI debug.

TMS

PU 10 k

Ω Input

JTAG Test Mode Select Input.

RTC_VDD

RTC supply. For proper operation of the Zdots,

this pin must be connected to the same power

source that powers the module (as it is done on

the Zilog® development platform).

EZ80CLK

Output

Synchronous CPU clock output.

I2CSCL

PU 4 k

Ω

Bidirectional

I2C Bus Clock.

GND

VSS/Ground (0 V).

I2CSDA

PU 4 k

Ω

Bidirectional

I2C Data Clock.

GND

Power

VSS/Ground (0 V).

FlashWE

PU 10 k

Ω Input

A Low enables a Write to external Flash memory

boot block area. If this pin is unconnected, the

Flash memory boot block area is Write-protected.

GND

VSS/Ground (0 V).

CS3

Output

Used on the eZ80190, eZ80L92, eZ80F92,

eZ80F93 devices and connected to the CS8900

EMAC.

DIS_IRDA

PU 10 k

Ω Input

A Low disables the onboard IRDA transceiver to

use PC0/PC1 UART pins externally.

RESET

PU 2 k

Ω

Bidirectional

Reset Output from module or push-button reset.

WAIT

PU 2 k

Ω

Input

Driving the WAIT pin Low forces the CPU to

provide additional clock cycles for an external

peripheral or external memory to complete its

Read or Write operation.

VCC

3.3 V supply input pin.

GND

VSS/Ground (0 V).

Table 2. Zdots Input/Output Connector Pin Identification* (Continued)

Pin No

Symbol

Pull

Up/Down

Signal

Direction

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